- 15 Jul, 2019 2 commits
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Matt Roper authored
Now that we distinguish between phy and port(ddi), mcc_port_to_ddc_pin should use the phy, not the DDI, for determining DDC pins. We're only converting the MCC function at the moment since EHL is the only platform that has configurations where port!=phy. Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190712221641.21031-1-matthew.d.roper@intel.comReviewed-by:
José Roberto de Souza <jose.souza@intel.com>
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Chris Wilson authored
GVT forces single port submission of individual requests. We do not enjoy the context amalgamation that the test depends upon for setting up the test (where port 0 has a large number of requests with a priority change somewhere in the middle). Under single request submission of gvt it is quite able for the preemption event to occur while another context is active and so there be a real need to act upon that preemption. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111108Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Acked-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190712082549.25053-1-chris@chris-wilson.co.uk
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- 13 Jul, 2019 11 commits
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Daniele Ceraolo Spurio authored
Get rid of them to avoid more users being added while the guc code transitions to use gt more than i915. Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Acked-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by:
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Daniele Ceraolo Spurio authored
We can get rid of a few more guc_to_i915 and start compartmentalizing interrupt management a bit more. We should be able to move more code in the future once the gt_pm code is also moved across to gt. Signed-off-by:
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Daniele Ceraolo Spurio authored
With our HW interface logic moving from i915 to gt and with GuC and HuC being part of the gt HW, it makes sense to use the intel_gt structure instead of i915 as our reference object in GuC/HuC paths. Signed-off-by:
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Daniele Ceraolo Spurio authored
All the intel_uc_* can now be moved to work on the intel_uc structure for better encapsulation of uc-related actions. Note: I've introduced uc_to_gt instead of uc_to_i915 because the aim is to move everything to be gt-focused in the medium term, so we would've had to replace it soon anyway. Signed-off-by:
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Daniele Ceraolo Spurio authored
Being part of the GT HW, it make sense to keep the guc/huc structures inside the GT structure. To help with the encapsulation work done by the following patches, both structures are placed inside a new intel_uc container. Although this results in code with ugly nested dereferences (i915->gt.uc.guc...), it saves us the extra work required in moving the structures twice (i915 -> gt -> uc). The following patches will reduce the number of places where we try to access the guc/huc structures directly from i915 and reduce the ugliness. Signed-off-by:
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Daniele Ceraolo Spurio authored
Both microcontrollers are part of the GT HW and are closely related to GT operations. To keep all the files cleanly together, they've been placed in their own subdir inside the gt/ folder Signed-off-by:
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Daniele Ceraolo Spurio authored
The 16-bit guc irq vector is unchanged across gens, the only thing that moved is its position (from the upper 16 bits of the PM regs to its own register). Instead of duplicating all defines and functions to handle the 2 different positions, we can work on the vector and shift it as appropriate. While at it, update the handler to work on intel_guc. Signed-off-by:
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Daniele Ceraolo Spurio authored
No functional change, just moving the guc_to_i915 from the caller into the irq function. This will help with the upcoming move of guc under intel_gt. Signed-off-by:
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Daniele Ceraolo Spurio authored
Instead of always checking in the device config is GuC and HuC are supported or not, we can save the state in the uc_fw structure and avoid going through i915 every time from the low-level uc management code. while at it FIRMWARE_NONE has been renamed to better indicate that we haven't started the fetch/load yet, but we might have already selected a blob. Signed-off-by:
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Daniele Ceraolo Spurio authored
The "misc" terminology doesn't clearly explain what we intend to cover in this phase. The only thing we used ot do in there apart from FW fetch was initializing the log workqueue, with the latter being required only in the very rare case where we enable the log relay. As we no longer create our own workqueue, piggybacking on the system_highpri_wq instead, we can rename the function to clarify that they only fetch/release the blobs. v2: only create log wq when needed (Michal), reword commit msg accordingly v3: after rebase the wq is gone, reword commit msg accordingly Signed-off-by:
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Chris Wilson authored
We only employ a single task for log capture, and created a workqueue for the purpose of ensuring we had a high priority queue for low latency. We can simply use the system_highpri_wq and avoid the complication with creating our own admist the maze of mutexes. (Currently we create the wq early before we even know we need it in order to avoid trying to create it on demand while we hold the logging mutex.) Signed-off-by:
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- 12 Jul, 2019 25 commits
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Chris Wilson authored
Having taken the first step in encapsulating the functionality by moving the related files under gt/, the next step is to start encapsulating by passing around the relevant structs rather than the global drm_i915_private. In this step, we pass intel_gt to intel_reset.c Signed-off-by:
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Lucas De Marchi authored
Tiger Lake has modular FIA bit indicating if we are using it, so add to the device info. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Stuart Summers <stuart.summers@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190712055706.12143-3-lucas.demarchi@intel.com
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Anusha Srivatsa authored
Some platforms may have Modular FIA. If Modular FIA is used in the SOC, then Display Driver will access the additional instances of FIA based on pre-assigned offset in GTTMADDR space. Each Modular FIA instance has its own IOSF Sideband Port ID and it houses only 2 Type-C Port. In SOC that has more than two Type-C Ports, there are multiple instances of Modular FIA. Gunit will need to use different destination ID when it access different pair of Type-C Port. The DFLEXDPSP register has Modular FIA bit starting on Tiger Lake. If Modular FIA is used in the SOC, this register bit exists in all the instances of Modular FIA. IOM FW is required to program only the MF bit in first FIA instance that houses the Type-C Port 0 and Port 1, for Display Driver to read from. v2 (Lucas): - Move all accesses to FIA to be contained in intel_tc.c, along with display_fia that is now called tc_phy_fia - Save the fia instance number on intel_digital_port, so we don't have to query if modular FIA is used on every access v3 (Lucas): Make function static v4 (Lucas): Move enum phy_fia to the header and use it in intel_digital_port (suggested by Ville) v5 (Lucas): Add comment about the mapping between FIA and TC port (suggested by Stuart) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Chris Wilson authored
With an explicit level, we can refactor the separate clear functions as a simple recursive function. The additional knowledge of the level allows us to spot when we can free an entire subtree at once. Signed-off-by:
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190712112725.2892-3-chris@chris-wilson.co.uk
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Chris Wilson authored
With an explicit level, we can refactor the separate cleanup functions as a simple recursive function. We take the opportunity to pass down the size of each level so that we can deal with the different sizes of top-level and avoid over allocating for 32/36-bit vm. Signed-off-by:
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Chris Wilson authored
intel_atomic_commit() is not for use internally, but only as an entry point from the core drm atomic helper (drm_atomic_commit). Squelches the warning for: drivers/gpu/drm/i915/display/intel_display.c:14148: warning: Function parameter or member '_state' not described in 'intel_atomic_commit' drivers/gpu/drm/i915/display/intel_display.c:14148: warning: Excess function parameter 'state' description in 'intel_atomic_commit' Signed-off-by:
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Ville Syrjälä authored
CH7511 doesn't update SINK_COUNT properly so in order to detect the device as connected we have to ignore SINK_COUNT. In order to have access to the quirk list early enough we must move the drm_dp_read_desc() call to happen earlier. We can also skip re-reading this on eDP since we know it won't change. Cc: David S. <david@majinbuu.com> Cc: Peteris Rudzusiks <peteris.rudzusiks@gmail.com> Tested-by:
Peteris Rudzusiks <peteris.rudzusiks@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105406Signed-off-by:
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Michal Wajdeczko authored
Using "enable_guc" modparam auto mode (-1) will let driver decide on which platforms and in which configuration we want to use GuC/HuC firmwares. Today driver will enable HuC firmware authentication by GuC only on Gen11+ platforms as HuC firmware is required to unlock advanced video codecs in media driver. Legacy platforms with GuC/HuC are not affected by this change as for them driver still defaults to disabled(0) in auto mode. Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Michal Wajdeczko authored
We are about to change default setting of "enable_guc" modparam from 0(disabled) to -1(auto). As we only want to turn on GuC/HuC on Gen11+, keep it off for older gens. Note that it would be still possible to enable GuC/HuC on these old platforms using explicit "enable_guc=2" modparam. Signed-off-by:
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Janusz Krzysztofik authored
Similar to the "_release" and "_remove" cases, consequently replace "_init" components of names of functions called from i915_driver_probe() with "_probe" suffixes for better code readability. Signed-off-by:
Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Reviewed-by:
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Janusz Krzysztofik authored
Similar to the "_release" case, consistently replace mixed "_cleanup"/"_fini"/"_fini_hw" components found in names of functions called from i915_driver_remove() with "_remove" or "_driver_remove" suffixes for better code readability. Signed-off-by:
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Janusz Krzysztofik authored
Replace mixed "_fini"/"_cleanup"/"_cleanup_hw" suffixes found in names of functions called from i915_driver_release() with "_release" suffix consistently. This provides better code readability, especially helpful when trying to work out which phase the code is in. Functions names starting with "i915_driver_", i.e., those defined in drivers/gpu/dri/i915/i915_drv.c, just have their "cleanup" or "fini" parts of their names replaced with the "_release" suffix, while names of functions coming from other source files have been suffixed with "_driver_release" to avoid ambiguity with other possible .release entry points. v2: early_probe pairs better with late_release (Chris) v3: fix typo in commit message (Joonas) Suggested-by:
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Janusz Krzysztofik authored
Use the "_probe" nomenclature not only in i915_driver_probe() helper name but also in other related function / variable names for consistency. Only the userspace exposed name of a related module parameter is left untouched. Signed-off-by:
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Janusz Krzysztofik authored
Current names of i915_driver_load/unload() functions originate in legacy DRM stubs. Reduce nomenclature ambiguity by renaming them to match their current use as helpers called from PCI entry points. Suggested by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Janusz Krzysztofik authored
Follow dim checkpatch recommendation so it doesn't complain on that now and again on header file modifications. v2: drop testing leftover (Chris) Signed-off-by:
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Chris Wilson authored
We can simplify our gtt walking code by comparing against NULL for scratch entries as opposed to looking up the distinct per-level scratch pointer. The only caveat is to remember to protect external parties and map the NULL to the scratch top pd. Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190712094327.24437-6-chris@chris-wilson.co.uk
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Chris Wilson authored
Each level has its own scratch. Make the levels more obvious by forgoing the fancy similarly names and replace them with a number. 0 is the bottom most level, the physical page used for actual data; 1+ are the page directories. Signed-off-by:
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Chris Wilson authored
The radix levels of each page directory are easily determined so replace the numerous hardcoded constants with precomputed derived constants. Signed-off-by:
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Chris Wilson authored
This will be useful to consolidate recursive code. Signed-off-by:
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Chris Wilson authored
In preparation for refactoring the free/clear/alloc, first move the code around so that we can avoid forward declarations in the next set of patches. Signed-off-by:
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Chris Wilson authored
The page directory extends the page table with the shadow entries. Make the page directory struct embed the page table for easier code reuse. Signed-off-by:
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Chris Wilson authored
We only use the dma pages for scratch, and so do not need to allocate the extra storage for the shadow page directory. v2: Refrain from reintroducing I915_PDES Signed-off-by:
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John Harrison authored
There is a debug message in the workaround initialisation path that reports how many entries were added of each type. However, whitelist workarounds exist for multiple engines but the type name is just 'whitelist'. Tvrtko suggested adding the engine name to make the message more useful. v2: Updated the similar message in the workaround reset selftest. Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> CC: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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John Harrison authored
Newer hardware supports extra feature in the whitelist registers. This patch updates the selftest to test that entries marked as read only are actually read only. v2: Removed all use of 'rsvd' for read-only registers to avoid ambiguous code or error messages. Signed-off-by:
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John Harrison authored
As per review feedback by Tvrtko, added a check that no invalid bits are being set in the whitelist flags fields. Also updated the read/write access definitions to make it clearer that they are an enum field not a set of single bit flags. Signed-off-by:
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- 11 Jul, 2019 2 commits
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José Roberto de Souza authored
This register definition changed from ICL and has now another meaning. Use the right bits on TGL. Signed-off-by:
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Lucas De Marchi authored
On TGL the port programming for combophy is very similar to ICL, so adapt the callers to possibly use the different register values. v2 (Lucas): Add TODO with about DPLL4 (requested by Ville) Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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