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- 13 May, 2012 2 commits
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Mark Brown authored
This gets us up to date with the recommended current kernel infrastructure and should transparently give us device tree interrupt bindings for any devices using the framework. If an explicit IRQ mapping is passed in then a legacy interrupt range is created, otherwise a simple linear mapping is used. Previously a mapping was mandatory so existing drivers should not be affected. A function regmap_irq_get_virq() is provided to allow drivers to map individual IRQs which should be used in preference to the existing regmap_irq_chip_get_base() which is only valid if a legacy IRQ range is provided. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Mark Brown authored
It's needed for freeing and for obtaining the IRQ base later on. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 11 Apr, 2012 1 commit
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Stephen Warren authored
Commit f01ee60f ("regmap: implement register striding") caused the compile errors below. Fix them. drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_sync_unlock': drivers/base/regmap/regmap-irq.c:62:12: error: 'map' undeclared (first use in this function) drivers/base/regmap/regmap-irq.c:62:12: note: each undeclared identifier is reported only once for each function it appears in drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_enable': drivers/base/regmap/regmap-irq.c:77:37: error: 'map' undeclared (first use in this function) drivers/base/regmap/regmap-irq.c: In function 'regmap_irq_disable': drivers/base/regmap/regmap-irq.c:85:37: error: 'map' undeclared (first use in this function) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 10 Apr, 2012 1 commit
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Stephen Warren authored
regmap_config.reg_stride is introduced. All extant register addresses are a multiple of this value. Users of serial-oriented regmap busses will typically set this to 1. Users of the MMIO regmap bus will typically set this based on the value size of their registers, in bytes, so 4 for a 32-bit register. Throughout the regmap code, actual register addresses are used. Wherever the register address is used to index some array of values, the address is divided by the stride to determine the index, or vice-versa. Error- checking is added to all entry-points for register address data to ensure that register addresses actually satisfy the specified stride. The MMIO bus ensures that the specified stride is large enough for the register size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 11 Mar, 2012 1 commit
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Paul Gortmaker authored
For files that are actively using linux/device.h, make sure that they call it out. This will allow us to clean up some of the implicit uses of linux/device.h within include/* without introducing build regressions. Yes, this was created by "cheating" -- i.e. the headers were cleaned up, and then the fallout was found and fixed, and then the two commits were reordered. This ensures we don't introduce build regressions into the git history. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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- 05 Dec, 2011 1 commit
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Mark Brown authored
Allows devices to discover their own interrupt without having to remember it themselves. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 28 Nov, 2011 1 commit
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Mark Brown authored
While the IRQ core doesn't currently support shared threaded interrupts that's no reason for drivers not to do their bit and report IRQ_NONE when they don't get an interrupt. This allows the core spurious/wedget interrupt detection support to do its thing. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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- 08 Nov, 2011 1 commit
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Mark Brown authored
There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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