- 03 Oct, 2014 2 commits
-
-
Ville Syrjälä authored
Clear the override bits to make sure the hardware manages the TX FIFO reset master on its own. v2: Squash with the earlier attempt at forcing the override bits Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
-
Ville Syrjälä authored
The register can house two different swing marging/deemph settings at once. However only one gets used based on some other bits. Make sure we set those bits correctly to make the hardware use the settings we provided. Signed-off-by:
-
- 02 Oct, 2014 3 commits
-
-
Rodrigo Vivi authored
Even though it's unliky, we should check each aux transaction not just the first one. Also commit ce31d9f4 Author: Rodrigo Vivi <rodrigo.vivi@intel.com> Date: Mon Sep 29 18:29:52 2014 -0400 drm/i915: preserve other DP_TEST_SINK bits. added a new aux transaction before the one which was checked. Fix this. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Todd Previte <tprevite@gmail.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
-
Daniel Vetter authored
Inspired by Ville constifying the send buffer for pach_aux. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:Daniel Vetter <daniel.vetter@intel.com>
-
Ville Syrjälä authored
Use pack_aux() to construct the PSR exit DPMS D0 AUX message, and use the defines from dp_dp_helper.h to populate the message contents. v2: Use sizeof() for message size (Jani) Use a generic loop to write EDP_PSR_AUX_DATA registers Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
-
- 01 Oct, 2014 9 commits
-
-
Daniel Vetter authored
This seems to have been accidentally lost in commit be62acb4 Author: Mika Kuoppala <mika.kuoppala@linux.intel.com> Date: Fri Aug 30 16:19:28 2013 +0300 drm/i915: ban badly behaving contexts Without this real gpu hangs only log output at info level, which gets filtered away by piglit's testrunner. v2: Tune down to notice level. Note that we need to add drm/i915 so that at least the automatic igt dmesg filtering still picks it up. v3: git add and lack of coffee don't mix well. v4: Message is in between hw and sw reset, so switch verb to continuous form. v5: Use i915_stop_rings_allow_warn for consistency. For Chris' case of injecting lots of hangs I guess we need to revamp this all anyway when merging. For now this should plug the regression for piglit testing mesa. v6: Make it compile (Mika). Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Kenneth Graunke <kenneth@whitecape.org> Reported-by:
Kenneth Graunke <kenneth@whitecape.org> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
-
Daniel Vetter authored
I've decided not to document the functions exported to the audio driver since really, they shouldn't exist ... v2: Improvements from Imre's review plus a few more spelling fixes I've spotted. Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
-
Daniel Vetter authored
Allows us to mark it static and so forgoe the kerneldoc for it. Note that intel_power_domains_fini is also called from failure paths in the driver load sequence. But the call to runtime_pm_disable for that is harmless since by default runtime pm is already disabled. v2: Augment the commit message as discussed with Imre on irc. Reviewed-by:
-
Daniel Vetter authored
I've decided to not move intel_display_port_power_domain because that's just a hack in our design ... Reviewed-by:
-
Daniel Vetter authored
- fini goes with init, so call it intel_power_domains_fini. While at it shovel some of the fini code that leaked out of it back in. - give power_enabled functions the verb _is_ to make the meaning clearer. Also use a __ prefix instead of _unlocked to really discourage users. - rename runtime_pm_init/fini to enable/disable since that's what they do. Reviewed-by:
-
Daniel Vetter authored
Geez is the audio hack ugly. Signed-off-by:
-
Daniel Vetter authored
Another layer of indirection for just an lpt-only w/a is a bit excessive. Reduce it. This was added in commit 7d708ee4 Author: Imre Deak <imre.deak@intel.com> Date: Wed Apr 17 14:04:50 2013 +0300 drm/i915: HSW: allow PCH clock gating for suspend Cc: Imre Deak <imre.deak@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
-
Daniel Vetter authored
Oh well. v2: Fix one more spelling fail Paulo spotted. Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
-
Daniel Vetter authored
So I think I've spotted a small gap in the frontbuffer tracking while discussing the logic with Paulo on irc: 1. Userspace schedules gpu rendering to the current frontbuffer. This gets tracked in dev_priv->fb_tracking.busy_bits. 2. We pageflip a fully rendered buffer before the frontbuffer rendering completes. 3. The request retiring will never clear busy_bits (since at retire time the old frontbuffer won't have obj->frontbuffer_bits set), so these bits now are stuck until someone again does a bit of frontbuffer tracking. If we clear stale busy_bits in flip_prepare this gap is closed. Reviewed-by:
-
- 30 Sep, 2014 5 commits
-
-
Daniel Vetter authored
SKL stage 1 patches still need polish so will likely miss the 3.18 merge window. We've decided to postpone to 3.19 so let's pull this in to make patch merging and conflict handling easier. Signed-off-by: -
Rodrigo Vivi authored
Sink crc was implemented based on dp 1.1 spec that had all TEST_SINK bits reserved reading all 0s. But when reviewing my latest changes on sink crc Todd warned me that on new specs we have other valid bits on this reg that we might want to preserve. Cc: Todd Previte <tprevite@gmail.com> Signed-off-by:
Todd Previte <tprevite@gmail.com> Signed-off-by:
-
Rodrigo Vivi authored
This WA affect BDW GT3 pre-production steppings. Signed-off-by:
-
Rodrigo Vivi authored
It will be usefull to specify w/a that affects only BDW GT3. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
-
Rodrigo Vivi authored
In some cases like when PSR just got enabled the panel need more vblank times to calculate CRC. I figured that out with the new PSR test cases facing some cases that I had a green screen but a blank CRC. Even with 2 vblank waits on kernel + 2 vblank waits on test case. So let's give up to 6 vblank wait time. However we now check for TEST_CRC_COUNT that shows when panel finished to calculate CRC and has it ready. v2: Jani pointed out attempts decrements was wrong and should never reach the error condition. And Daniel pointed out that EIO is more appropriated than EGAIN. Also I realized that I have to read test_crc_count after setting test_sink v3: Rebase and adding error message Cc: Todd Previte <tprevite@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
-
- 29 Sep, 2014 4 commits
-
-
Rodrigo Vivi authored
BDW display - DP buffer translation values changed to give better margin. Further change to entry 6; set dword 0 bit 31=1. Both changes were approved already but this one didn't landed BSpec yet this is why it is in a separated patch. Making reviewer's life easier. Also alowing separated tests and any future bisect that might be needed. Reference: Predator r74080 / HSD 4394389 v2: Arthur noticed I was changing the wrong bit. Cc: Arthur Runyan <arthur.j.runyan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Arthur Runyan <arthur.j.runyan@intel.com> Signed-off-by:
-
Rodrigo Vivi authored
Reference: Predator r73977 / HSD 4394389 Cc: Arthur Runyan <arthur.j.runyan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
-
Rodrigo Vivi authored
Let's make sure PSR is propperly disabled before to re-enabled it. According to Spec, after disabled PSR CTL, the Idle state might occur up to 24ms, that is one full frame time (1/refresh rate), plus SRD exit training time (max of 6ms), plus SRD aux channel handshake (max of 1.5ms). So if something went wrong PSR will be disabled until next full enable/disable setup. v2: The 24ms above takes in account 16ms for refresh rate on 60Hz mode. However on low frequency modes this can take longer. So let's use 50ms for safeness. v3: Move wait out of psr.lock critical area. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
-
Rodrigo Vivi authored
The sw cache clean on BDW is a tempoorary workaround because we cannot set cache clean on blt ring with risk of hungs. So we are doing the cache clean on sw. However we are doing much more than needed. Not only when using blt ring. So, with this extra w/a we minimize the ammount of cache cleans and call it only on same cases that it was being called on gen7. The traditional FBC Cache clean happens over LRI on BLT ring when there is a frontbuffer touch happening. frontbuffer tracking set fbc_dirty variable to let BLT flush that it must clean FBC cache. fbc.need_sw_cache_clean works in the opposite information direction of ring->fbc_dirty telling software on frontbuffer tracking to perform the cache clean on sw side. v2: Clean it a little bit and fully check for Broadwell instead of gen8. v3: Rebase after frontbuffer organization. v4: Wiggle confused me. So fixing v3! Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
-
- 24 Sep, 2014 17 commits
-
-
Rodrigo Vivi authored
The panel has to be reconfigured only when it really loose the power. The traditional enable/disable sequence already take care of this so we can minimize the time spend on every re-enable. Signed-off-by:
-
Damien Lespiau authored
Gen9 is different enough (for instance, fetching the memory latency values is different from ILK+) to not take the HAS_PCH_SPLIT() branch, so let's prefer a clean separation. v2: Rebase on top of the broadwell_init_clock_gating() name change Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
-
Damien Lespiau authored
It can be handy to get the number of planes for this pipe, ie including the primary plane to loop over them. Introduce a little function to do so. Reviewed-by:
-
Damien Lespiau authored
This can be useful to declare structures around pipes and planes and don't have to go back auditing the code if the next platorm bump that number. Reviewed-by:
-
Damien Lespiau authored
Let's put to good use the new PLANE_CTL macros. Reviewed-by:
-
Damien Lespiau authored
SKL Uses the same hardware for all planes now, so called "universal" planes. Ie both the primary planes and sprite planes share the same logic. This patch implements the drm_plane vfuncs for "sprites" ie planes that aren't the primary plane. v2: Couple of fixes: - Actually enabled the planes and fix the plane number Reviewed-by:
-
Damien Lespiau authored
On Skylake, we use plane1 as primary plane and plane2/3 as sprite planes. v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. Reviewed-by: -
Damien Lespiau authored
Reviewed-by:
-
Damien Lespiau authored
Reviewed-by:
-
Damien Lespiau authored
Reviewed-by:
-
Satheeshakrishna M authored
This patch implements detection of SPT and SPT-LP PCH devices. v2: Added HAS_PCH_SPT macro Reviewed-by:
Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by:
-
Damien Lespiau authored
To accomodate the extra planes, the bit definitions were shuffled around a bit. v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. v3: Rebase after yet another change int that area (done with wiggle) Reviewed-by: -
Satheeshakrishna M authored
Extending BDW implementation to gen9. Pipe B/C interrupt restoration after exiting LPSP. v2: Fix minor rebasing conflict. Reviewed-by:
-
Satheeshakrishna M authored
Extending the BDW backlight implementation to SKL. Reviewed-by:
-
Satheeshakrishna M authored
Set gen 9 function pointers for eld write and global resource. Implementation remains same as HSW. v2: Rebase on top of Sonika's untangling of the if/else ladder (Damien) Reviewed-by:
-
Satheeshakrishna M authored
Pipe misc programming in gen9 is similar to BDW. Extending the BDW implementation to gen 9. Reviewed-by:
-
Damien Lespiau authored
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com Signed-off-by:
-
