- 17 Oct, 2019 9 commits
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Bhawanpreet Lakha authored
Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Bhawanpreet Lakha authored
Signed-off-by:
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Roman Li authored
[Why] Earlier changes to support configurable aux timeout caused dc init failure on vega due to missing reg defs. Needs to be disabled until implemented for vega. [How] Set extended aux timeout cap for vega to false. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Signed-off-by:
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abdoulaye berthe authored
[Description] 1-add configurable timeout support to aux engine. 2-add timeout support field to dc_caps 3-add reg_key to override extended timeout support Signed-off-by:
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abdoulaye berthe authored
1-add timeout length and multiplier fields to aux_control1 register 2-update access mechanism from macro constructed name to uint32_t defined addresses. 3-define registers and field per asic family Signed-off-by:
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chen gong authored
smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch. As to when GPU get into "GFXoff" will be up to drawing load. So we can not sure which state GPU should be in after enable gfxoff feature. Signed-off-by:
chen gong <curry.gong@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
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Kenneth Feng authored
In some cases, display fixes memory clock frequency to a high value rather than the natural memory clock switching. When we comes back from s3 resume, the request from display is not reset, this causes the bug which makes the memory clock goes into a low value. Then due to the insuffcient memory clock, the screen flicks. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Prike Liang authored
Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response. The patch can fix VCN IB test failed and DAL get dispaly count failed issue. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Prike Liang authored
Before disable gfx pipeline power gating need check the flag AMD_PG_SUPPORT_GFX_PIPELINE. Signed-off-by:
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- 15 Oct, 2019 31 commits
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Ahzo authored
This fixes kernel NULL pointer dereferences on shutdown: RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu] RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu] Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Ahzo <Ahzo@tutanota.com> Signed-off-by:
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Alex Deucher authored
Use BACO to reset the GPU if supported on SMU7 based dGPUs. v2: don't use baco on CI parts Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Wire up the powerplay callbacks for for BACO for smu7 devices. Reviewed-by:
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Alex Deucher authored
Several of the BACO functions are common across smu7-based asics. Split the common code out. Reviewed-by:
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Alex Deucher authored
This adds BACO support for CI asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Fiji asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for VegaM asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Polaris asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Iceland asics. Reviewed-by:
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Alex Deucher authored
This adds BACO support for Tonga. Reviewed-by:
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Alex Deucher authored
This adds core support for BACO on pre-vega asics. Reviewed-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Add support for vega20 when the swSMU path is used. Reviewed-by:
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Alex Deucher authored
It was a vega20 specific hack. Check if we are in reset and what reset method we are using. Reviewed-by:
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Alex Deucher authored
Use the base class rather than the specific class and drop the second loop. Reviewed-by:
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Alex Deucher authored
Move it into the caller. There are cases were we don't want it. We need it for hibernation, but we don't need it for runtime pm, so drop it for runtime pm. Reviewed-by:
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Alex Deucher authored
for amdgpu_device_suspend. This follows the logic in the resume path. Reviewed-by:
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Alex Deucher authored
This reverts commit 6f7fe9a9. This breaks some boards. Maybe just enable this on PPC for now? Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205147Signed-off-by:
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Hersen Wu authored
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config, there is build error. struct dpm_clocks shoud not be guarded. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Hersen Wu authored
enable dc get dmp clock table and set dcn watermarks via pplib. Signed-off-by:
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Andrey Grodzovsky authored
Ignre the ERREVENT_ATHUB_INTERRUPT for systems without RAS. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-and-tested-by:
Jack Zhang <Jack.Zhang1@amd.com> Acked-by:
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Philip Yang authored
user_pages array should always be freed after validation regardless if user pages are changed after bo is created because with HMM change parse bo always allocate user pages array to get user pages for userptr bo. v2: remove unused local variable and amend commit v3: add back get user pages in gem_userptr_ioctl, to detect application bug where an userptr VMA is not ananymous memory and reject it. Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Tested-by:
Joe Barnett <thejoe@gmail.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Hersen Wu authored
there are two paths for renoir dc access smu. one dc access smu directly using bios smc interface: set disply, dprefclk, etc. another goes through pplib for get dpm clock table and set watermmark. Signed-off-by:
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Evan Quan authored
Enable runtime VCN DPM on/off on Arcturus. Signed-off-by:
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Kenneth Feng authored
Bug fix for pcie paramerers override on swsmu. Below is a scenario to have this problem. pptable definition on pcie dpm: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:4, pcie lanes: *16 Then if we have a system only have the capbility: pcie gen speed: 3, pcie lanes: *8, we will override dpm 1 to pcie gen speed 3, pcie lanes *8. But the code skips the dpm 0 configuration. So the real pcie dpm parameters are: 0 -> pcie gen speed:1, pcie lanes: *16 1 -> pcie gen speed:3, pcie lanes: *8 Then the wrong pcie lanes will be toggled. Signed-off-by:
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Emily Deng authored
When index is 1, need to set compute ring timeout for sriov and passthrough. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Christian König authored
When we allocate new page tables under memory pressure we should not evict old ones. Signed-off-by:
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