- 06 Dec, 2017 40 commits
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Andrew Jiang authored
Make it so that differing dcc and plane size fields don't necessarily result in a full update, along with upscaling modes. This allows us to save some unnecessary full updates. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andrew Jiang authored
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Eric Yang authored
output signal used to be a public member to be used by DM to override the stream signal. Now since there is no longer separation between public and private part of stream, they are combined. The overriding was not working properly as well, which is addressed by this change Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Harry Wentland authored
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Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
arr_points[1] and [2] were duplicated. Remove the extra one. If we ever need more points we can add them but the current state of affairs is confusing. Signed-off-by:
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Tony Cheng authored
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Eric Yang authored
Temporary solution to fix gamma adjustment not working. Signed-off-by:
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Yongqiang Sun authored
New scaler parameter assign to dpp is after early return, cause next flip scaler not program. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Tony Cheng authored
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Eric Bernstein authored
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Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Ken Chalmers authored
The ALLOW_SR registers might not always be available. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
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SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Hersen Wu authored
SMU can future lower voltages in long idle case when all display is off. If all display output is turned off via DPMS, send display_count = 0 after all output are turned off. otherwise send display_count msg before turning on display to make sure SMU exit S0i2 state. before is not neccessary as we are out of S0i2 when driver execute code, but send message before anyways for correctness. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Yongqiang Sun authored
Optimized front end initial sequence, reset MPC module properly. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
When new coefficients match cached we would skip setting regamma mode Also, when doing a stream update we would program regamma for all pipes, even thos that are not yet powered on. This resulted in never setting regamma since we would cache before the pipe is powered. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
Trying to align with kernel coding style and make it a bit more readable. Signed-off-by:
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Yongqiang Sun authored
There are different code to disable front end, it is difficult to debug and adding new process. This refactor makes all disable front end call the same functions. Signed-off-by:
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Tony Cheng authored
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Yue Hin Lau authored
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Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Tony Cheng authored
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Yue Hin Lau authored
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Eric Bernstein authored
Added a function to blank data using OPP DPG. Clean up code to prepare for pseudocode review with HW. Signed-off-by:
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Tony Cheng authored
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Dmytro Laktyushkin authored
This saves us about 5000 reg writes per full update. This translates to about 40000 writes over the course of single eDP bootup. Signed-off-by:
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Andrew Jiang authored
dc_link is at a higher level than link_encoder, and we only want higher-level components to be able to access lower-level ones, not the other way around. Signed-off-by:
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Harry Wentland authored
Previous code threw a warning about misleading indentation Signed-off-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Yongqiang Sun authored
Clear OPTC underflow status when init_hw. Signed-off-by:
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Yongqiang Sun authored
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Eric Yang authored
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Yue Hin Lau authored
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Eric Bernstein authored
Also move some register definitions to common DCN regs. Signed-off-by:
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Tony Cheng authored
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Yue Hin Lau authored
no logic change Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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