Skip to content

L
linux
Switch branch/tag
  1. 18 Oct, 2013 3 commits
    • Trent Piepho's avatar
      spi: spi-mxs: Always clear INGORE_CRC, to keep CS asserted · 75e73fa2
      Trent Piepho authored 
      INGORE_CRC, better named DEASSERT_CS, should be cleared on all tranfers
except the last.  So instead of only clearing it on the first transfer, we
can just always clear it.  It will set on the last transfer.

This removes the only use of the "first" flag in the transfer functions, so
that flag can be then be removed.
Signed-off-by: default avatarTrent Piepho <tpiepho@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      75e73fa2
    • Trent Piepho's avatar
      spi: spi-mxs: Remove mxs_spi_enable and mxs_spi_disable · f5bc7384
      Trent Piepho authored 
      These functions consist of nothing but one single writel call and are
only called once.  And the names really aren't accurate or clear,
since they don't enable or disble SPI.  Rather they set the bit that
controls the state of CS at the end of transfer.  It easier to follow
the code to just set this bit with a writel() along with all the other
bits being set in the same function.
Signed-off-by: default avatarTrent Piepho <tpiepho@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      f5bc7384
    • Trent Piepho's avatar
      spi: spi-mxs: Always set LOCK_CS · 58f46e41
      Trent Piepho authored 
      There are two bits which control the CS line in the CTRL0 register:
LOCK_CS and IGNORE_CRC.  The latter would be better named DEASSERT_CS
in SPI mode.

LOCK_CS keeps CS asserted though the entire transfer.  This should
always be set.  The DMA code will always set it, explicitly on the
first segment of the first transfer, and then implicitly on all the
rest by never clearing the bit from the value read from the ctrl0
register.

The PIO code will explicitly set it for the first transfer, leave it
set for intermediate transfers, and then clear it for the final
transfer.  It should not clear it.

The only reason to not set LOCK_CS would be to attempt an altered
protocol where CS pulses between each word.  Though don't get your
hopes up if you want to do this, as the hardware doesn't appear to do
this in any sane manner.  It appears to be related to the hardware
FIFO fill level.

The code can be simplified by just setting LOCK_CS once and then not
needing to deal with it at all in the PIO and DMA transfer functions.
Signed-off-by: default avatarTrent Piepho <tpiepho@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
      58f46e41
  3. 13 Oct, 2013 17 commits
  5. 12 Oct, 2013 10 commits
  7. 11 Oct, 2013 10 commits
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7