- 09 Jun, 2017 40 commits
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Christopher Bostic authored
Add an engine driver to expose a "hub" FSI master - which has a set of control registers in the engine address space, and uses a chunk of the slave address space for actual FSI communication. Additional changes from Jeremy Kerr <jk@ozlabs.org>. Signed-off-by:
Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by:
Jeremy Kerr <jk@ozlabs.org> Signed-off-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Christopher Bostic authored
Create a simple SCOM engine device driver that reads and writes its control registers via an FSI bus. Includes changes from Edward A. James <eajames@us.ibm.com>. Signed-off-by:
Edward A. James <eajames@us.ibm.com> Signed-off-by:
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Jeremy Kerr authored
Trace low level input/output GPIO operations. Signed-off-by:
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Christopher Bostic authored
Implement a FSI master using GPIO. Will generate FSI protocol for read and write commands to particular addresses. Sends master command and waits for and decodes a slave response. Includes changes from Edward A. James <eajames@us.ibm.com> and Jeremy Kerr <jk@ozlabs.org>. Signed-off-by:
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Christopher Bostic authored
Add info for sysfs scan file in Documentaiton ABI/testing Signed-off-by:
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Jeremy Kerr authored
This change implements error handling in the FSI core, by cleaining up and retrying failed operations, using the SISC, TERM and BREAK facilities. Signed-off-by:
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Jeremy Kerr authored
Trace low level read and write FSI bus operations. Signed-off-by:
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Jeremy Kerr authored
Allow drivers to access the slave address ranges. Signed-off-by:
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Jeremy Kerr authored
This change adds a 'raw' file for reads & writes, and a 'term' file for the TERM command, and a 'break' file for issuing a BREAK. Signed-off-by:
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Christopher Bostic authored
Add driver_register and driver_unregister wrappers for FSI. Signed-off-by:
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Christopher Bostic authored
Add fsi master gpio device tree binding documentation. Includes changes from Jeremy Kerr <jk@ozlabs.org>. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Christopher Bostic authored
Allow a master to undo a previous scan. Should a master scan a bus twice it will need to ensure it doesn't double register any previously detected device. Signed-off-by:
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Jeremy Kerr authored
This change introduces the fsi device API: simple read, write and peek accessors for the devices' address spaces. Includes contributions from Christopher Bostic <cbostic@linux.vnet.ibm.com> and Edward A. James <eajames@us.ibm.com>. Signed-off-by:
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Jeremy Kerr authored
Now that we have fsi_slave devices, scan each for endpoints, and register them on the fsi bus. Includes contributions from Christopher Bostic <cbostic@linux.vnet.ibm.com>. Signed-off-by:
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Christopher Bostic authored
Set CFAM to appropriate ID so that the controlling master can manage link memory ranges. Add slave engine register definitions. Includes changes from Jeremy Kerr <jk@ozlabs.org>. Signed-off-by:
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Jeremy Kerr authored
Implement fsi_slave_init: if we can read a chip ID, create fsi_slave devices and register with the driver core. Includes changes from Christopher Bostic <cbostic@linux.vnet.ibm.com>. Signed-off-by:
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Christopher Bostic authored
Enable each link and send a break command, and try to detect a slave by reading from the SMODE register. Signed-off-by:
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Jeremy Kerr authored
Introduce functions to perform reads/writes on the slave address space; these simply pass the request on the slave's master with the correct link and slave ID. We implement these on top of similar helpers for the master. Signed-off-by:
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Jeremy Kerr authored
Add a little helper for crc4 calculations. This works 4-bits-at-a-time, using a simple table approach. We will need this in the FSI core code, as well as any master implementations that need to calculate CRCs in software. Signed-off-by:
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Jeremy Kerr authored
When a new fsi master is added, we will need to scan its links, and slaves attached to those links. This change introduces a little shell to iterate the links, which we will populate with the actual slave scan in a later change. Signed-off-by:
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Jeremy Kerr authored
Add the initial fsi slave device, which is private to the core code. This will be a child of the master, and parent to endpoint devices. Signed-off-by:
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Jeremy Kerr authored
Add a `struct fsi_master` to represent a FSI master controller. FSI master drivers register one of these structs to provide device-specific of the standard operations: read/write/term/break and link control. Includes changes from Edward A. James <eajames@us.ibm.com> & Jeremy Kerr <jk@ozlabs.org>. Signed-off-by:
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Roberto Pereira authored
Disable Network file system support. Reviewed-at: https://android-review.googlesource.com/#/c/409559/Signed-off-by:
Roberto Pereira <rpere@google.com> [AmitP: cherry-picked this change from Android common kernel and updated commit message] Signed-off-by:
Amit Pundir <amit.pundir@linaro.org> Signed-off-by:
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Chenbo Feng authored
Add CONFIG_CGROUP_BPF as a default configuration in android base config since it is used to replace XT_QTAGUID in future. Reviewed-at: https://android-review.googlesource.com/#/c/400374/Signed-off-by:
Chenbo Feng <fengc@google.com> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by:
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Greg Kroah-Hartman authored
This adds CONFIG_MODULES, CONFIG_MODULE_UNLOAD, and CONFIG_MODVERSIONS which are required by the O release. Reviewed-at: https://android-review.googlesource.com/#/c/364554/Signed-off-by:
Greg Kroah-Hartman <gregkh@google.com> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by:
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Greg Kroah-Hartman authored
This adds CONFIG_IKCONFIG and CONFIG_IKCONFIG_PROC options, which are a requirement for the O release. Reviewed-at: https://android-review.googlesource.com/#/c/364553/Signed-off-by:
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Sami Tolvanen authored
Enable CPU domain PAN to ensure that normal kernel accesses are unable to access userspace addresses. Reviewed-at: https://android-review.googlesource.com/#/c/334035/Signed-off-by:
Sami Tolvanen <samitolvanen@google.com> [AmitP: cherry-picked this change from Android common kernel, updated the commit message and re-placed the CONFIG_STRICT_KERNEL_RWX config in sorted order] Signed-off-by:
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Max Shi authored
Turn off the two kernel configs to disable related system ABI. Reviewed-at: https://android-review.googlesource.com/#/c/264976/Signed-off-by:
Max Shi <meixuanshi@google.com> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by:
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Sami Tolvanen authored
Enable PAN emulation using TTBR0_EL1 switching. Reviewed-at: https://android-review.googlesource.com/#/c/325997/Signed-off-by:
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Jeff Vander Stoep authored
If compiler has stack protector support, set CONFIG_CC_STACKPROTECTOR_STRONG. Reviewed-at: https://android-review.googlesource.com/#/c/238388/Signed-off-by:
Jeff Vander Stoep <jeffv@google.com> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by:
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Leo Yan authored
Add debug unit on Qualcomm msm8916 based platforms, including the DragonBoard 410c board. Signed-off-by:
Leo Yan <leo.yan@linaro.org> Reviewed-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by:
Andy Gross <andy.gross@linaro.org> Signed-off-by:
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Leo Yan authored
Bind debug module driver for Hi6220. Signed-off-by:
Wei Xu <xuwei5@hisilicon.com> Signed-off-by:
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Leo Yan authored
Coresight includes debug module and usually the module connects with CPU debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has description for related info in "Part H: External Debug". Chapter H7 "The Sample-based Profiling Extension" introduces several sampling registers, e.g. we can check program counter value with combined CPU exception level, secure state, etc. So this is helpful for analysis CPU lockup scenarios, e.g. if one CPU has run into infinite loop with IRQ disabled. In this case the CPU cannot switch context and handle any interrupt (including IPIs), as the result it cannot handle SMP call for stack dump. This patch is to enable coresight debug module, so firstly this driver is to bind apb clock for debug module and this is to ensure the debug module can be accessed from program or external debugger. And the driver uses sample-based registers for debug purpose, e.g. when system triggers panic, the driver will dump program counter and combined context registers (EDCIDSR, EDVIDSR); by parsing context registers so can quickly get to know CPU secure state, exception level, etc. Some of the debug module registers are located in CPU power domain, so this requires the CPU power domain stays on when access related debug registers, but the power management for CPU power domain is quite dependent on SoC integration for power management. For the platforms which with sane power controller implementations, this driver follows the method to set EDPRCR to try to pull the CPU out of low power state and then set 'no power down request' bit so the CPU has no chance to lose power. If the SoC has not followed up this design well for power management controller, the user should use the command line parameter or sysfs to constrain all or partial idle states to ensure the CPU power domain is enabled and access coresight CPU debug component safely. Signed-off-by:
Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by:
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Leo Yan authored
This is refactor to add function of_coresight_get_cpu(), so it's used to retrieve CPU id for coresight component. Finally can use it as a common function for multiple places. Suggested-by:
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Suzuki K Poulose authored
The of_get_coresight_platform_data iterates over the possible CPU nodes to find a given cpu phandle. However it does not drop the reference to the node pointer returned by the of_get_coresight_platform_data. This patch also introduces another minor fix is to use of_cpu_device_node_get() to replace of_get_cpu_node(). Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Leo Yan authored
Update document file entries for Coresight debug module. Signed-off-by:
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Leo Yan authored
Add coresight_cpu_debug.enable to kernel-parameters.txt, this flag is used to enable/disable the CPU sampling based debugging. Signed-off-by:
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Leo Yan authored
Add detailed documentation for Coresight CPU debug driver, which contains the info for driver implementation, Mike Leach excellent summary for "clock and power domain". At the end some examples on how to enable the debugging functionality are provided. Suggested-by:
Mike Leach <mike.leach@linaro.org> Signed-off-by:
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Leo Yan authored
According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by:
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Robin Murphy authored
Before making any DMA API calls, the ETR driver should really be setting its masks to ensure that DMA is possible. Especially since it can address more than the 32-bit default mask set by the AMBA bus code. Signed-off-by:
Robin Murphy <robin.murphy@arm.com> Tested-by:
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