- 16 Dec, 2014 4 commits
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Tero Kristo authored
The new usage of determine_rate and set_rate_and_parent calls for OMAP DPLLs assumes the DPLLs must have two parents defined, even if it is the same clock. Legacy clock data did not fullfill this requirement and caused a boot crash. Fixed by adding the missing parent information to the DPLL clocks. Signed-off-by:
Tero Kristo <t-kristo@ti.com> Fixes: 2e1a7b01 ("ARM: OMAP3+: DPLL: use determine_rate() and...") Cc: Paul Walmsley <paul@pwsan.com> Acked-by:
Tony Lindgren <tony@atomide.com> Tested-by:
Kevin Hilman <khilman@linaro.org> Reported-by:
Michael Turquette <mturquette@linaro.org>
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Tero Kristo authored
While the change for determine_rate clock operation was merged, the OMAP counterpart using these calls was overlooked for some reason, and caused boot failures on at least OMAP4 platforms. Fixed by updating the DPLL API calls to use the new parameters. Signed-off-by:
Paul Walmsley <paul@pwsan.com> Tested-by:
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Michael Turquette authored
Merge tag 'for-v3.19/omap-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into tmp Some OMAP clock/hwmod patches for v3.19. Most of the patches are clock-related. The DPLL implementation is changed to better align to the common clock framework. There is also a patch that removes a few lines from the hwmod code - this patch should have no functional effect. Basic build, boot, and PM test logs for these patches can be found here: http://www.pwsan.com/omap/testlogs/omap-a-for-v3.19/20141113094101/
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Stephen Boyd authored
Commit 6314b679 (clk: Don't hold prepare_lock across debugfs creation, 2014-09-04) forgot to update one place where we hold the prepare_lock while creating debugfs directories. This means we still have the chance of a deadlock that the commit was trying to fix. Actually fix it by moving the debugfs creation outside the prepare_lock. Cc: <stable@vger.kernel.org> # 3.18 Reported-by:
Russell King <rmk+kernel@arm.linux.org.uk> Fixes: 6314b679 "clk: Don't hold prepare_lock across debugfs creation" Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Reviewed-by:
Thomas Gleixner <tglx@linutronix.de> Signed-off-by:
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- 11 Dec, 2014 2 commits
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git://linuxtv.org/snawrocki/samsungMichael Turquette authored
- exynos4415 and exynos audio subsystem clk driver (build with PM_SLEEP disabled, resource release) fixes - minor cleanups in drivers/clk/samsung/clk.c (spelling, includes) - modification of the exynos4 HDMI PHY clock definition to model dependency of "sclk_hdmiphy" on the "hdmi" clock
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Wei Yongjun authored
Fixes the following sparse warnings: drivers/clk/mmp/clk-frac.c:113:6: warning: symbol 'clk_factor_init' was not declared. Should it be static? Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by:
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- 04 Dec, 2014 1 commit
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Tomeu Vizoso authored
This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by:
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- 03 Dec, 2014 4 commits
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Tomeu Vizoso authored
Instead of struct clk, as this should be only used by providers. Signed-off-by:
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Tomeu Vizoso authored
As it's only used internally, in drivers/clk/clk.c. Signed-off-by:
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Tomeu Vizoso authored
As __clk_release could call kfree on clk and then we wouldn't have a safe way of getting the module that owns the clock. Signed-off-by:
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Tomeu Vizoso authored
Signed-off-by:
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- 02 Dec, 2014 6 commits
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Krzysztof Kozlowski authored
During driver unbind the syscore ops were not unregistered which lead to double add on syscore list: $ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/unbind $ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/bind [ 1463.044061] ------------[ cut here ]------------ [ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36 __list_add+0x8c/0xc0() [ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84. [ 1463.061625] Modules linked in: [ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: G W 3.18.0-rc5-next-20141121-00005-ga8fab06eab42-dirty #1022 [ 1463.075338] [<c0014e2c>] (unwind_backtrace) from [<c0011d80>] (show_stack+0x10/0x14) [ 1463.083046] [<c0011d80>] (show_stack) from [<c048bb70>] (dump_stack+0x70/0xbc) [ 1463.090236] [<c048bb70>] (dump_stack) from [<c00233d4>] (warn_slowpath_common+0x74/0xb0) [ 1463.098295] [<c00233d4>] (warn_slowpath_common) from [<c00234a4>] (warn_slowpath_fmt+0x30/0x40) [ 1463.106962] [<c00234a4>] (warn_slowpath_fmt) from [<c020fe80>] (__list_add+0x8c/0xc0) [ 1463.114760] [<c020fe80>] (__list_add) from [<c0282094>] (register_syscore_ops+0x30/0x3c) [ 1463.122819] [<c0282094>] (register_syscore_ops) from [<c0392f20>] (exynos_audss_clk_probe+0x36c/0x460) [ 1463.132091] [<c0392f20>] (exynos_audss_clk_probe) from [<c0283084>] (platform_drv_probe+0x48/0xa4) [ 1463.141013] [<c0283084>] (platform_drv_probe) from [<c0281a14>] (driver_probe_device+0x13c/0x37c) [ 1463.149852] [<c0281a14>] (driver_probe_device) from [<c0280560>] (bind_store+0x90/0xe0) [ 1463.157822] [<c0280560>] (bind_store) from [<c027fd10>] (drv_attr_store+0x20/0x2c) [ 1463.165363] [<c027fd10>] (drv_attr_store) from [<c0143898>] (sysfs_kf_write+0x4c/0x50) [ 1463.173252] [<c0143898>] (sysfs_kf_write) from [<c0142c80>] (kernfs_fop_write+0xbc/0x198) [ 1463.181395] [<c0142c80>] (kernfs_fop_write) from [<c00e2be0>] (vfs_write+0xa0/0x1a8) [ 1463.189104] [<c00e2be0>] (vfs_write) from [<c00e2f00>] (SyS_write+0x40/0x8c) [ 1463.196122] [<c00e2f00>] (SyS_write) from [<c000f2a0>] (ret_fast_syscall+0x0/0x48) [ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]--- [ 1463.208244] exynos-audss-clk 3810000.audss-clock-controller: setup completed Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Fixes: 1241ef94 ("clk: samsung: register audio subsystem clocks using common clock framework") Cc: <stable@vger.kernel.org> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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Andrzej Hajda authored
sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock. The patch models this dependency using parent/child hirerarchy. The patch fixes issue with system hangs during mixer device access, mixer uses sclk_hdmiphy descendant clock. Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
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Krzysztof Kozlowski authored
Fix following build errors when PM_SLEEP is disabled (e.g. by disabling SUSPEND and HIBERNATION): drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_init’: drivers/clk/samsung/clk-exynos4415.c:982:2: error: ‘exynos4415_ctx’ undeclared (first use in this function) drivers/clk/samsung/clk-exynos4415.c:982:2: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_dmc_init’: drivers/clk/samsung/clk-exynos4415.c:1123:2: error: ‘exynos4415_dmc_ctx’ undeclared (first use in this function) make[3]: *** [drivers/clk/samsung/clk-exynos4415.o] Error 1 Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
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Pankaj Dubey authored
Let's remove unnecessary include of header files from clk.h and add required one in clk.c Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> [s.nawrocki@samsung.com: dropped removal of '#include <linux/syscore_ops.h>'] Signed-off-by:
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Pankaj Dubey authored
Remove unnecessary CONFIG_OF from samsung/clk.c. Signed-off-by:
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Pankaj Dubey authored
Fix a typo in comment section of "struct samsung_clk_provider". Signed-off-by:
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- 29 Nov, 2014 2 commits
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Michael Turquette authored
Merge tag 'ib-mfd-regulator-clk-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into clk-next Immutable branch between MFD, Regulator and Clk, due for v3.19
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Michael Turquette authored
Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next - clock phase setting capability for the rk3288 mmc clocks - pll init to allow syncing to actual rate table values - some more exported clocks - fixes for some clocks (typos etc) all of them not yet used in actual drivers
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- 27 Nov, 2014 3 commits
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Alexandru M Stan authored
This patch adds the 2 physical clocks for the mmc (drive and sample). They're mostly there for the phase properties, but they also show the true clock (by dividing by RK3288_MMC_CLKGEN_DIV). The drive and sample phases are generated by dividing an upstream parent clock by 2, this allows us to adjust the phase by 90 deg. There's also an option to have up to 255 delay elements (40-80 picoseconds long). This driver uses those elements (under the assumption that they're 60 ps long) to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as 90 deg if the delay elements are as big as 80 ps, so a finer division (smaller than 22.5) was not picked because the phase might not be monotonic anymore. Suggested-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Alexandru M Stan <amstan@chromium.org> Signed-off-by:
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Alexandru M Stan authored
These clocks represent the physical clocks (including phases) and they will later be used for clock phase tuning. Suggested-by:
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Sonny Rao authored
This exposes the clock that comes out of the i2s block which generally goes to the audio codec. Signed-off-by:
Sonny Rao <sonnyrao@chromium.org> [removed CLK_SET_RATE_PARENT from original patch] Signed-off-by:
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- 26 Nov, 2014 3 commits
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Jeff Chen authored
The DMC clocks need to be turned off at runtime. Use the newly assigned clock IDs to export them. Signed-off-by:
Jeff Chen <cym@rock-chips.com> [dianders: split into two patches; adjusted commit msg] Signed-off-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
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Jeff Chen authored
The DMC clocks need to be turned off at runtime, so we should have IDs so we can export them. Signed-off-by:
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kbuild test robot authored
drivers/clk/clk-s2mps11.c:181:2-3: Unneeded semicolon Removes unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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- 25 Nov, 2014 10 commits
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Chanwoo Choi authored
This patch adds the binding documentation for Samsung S2MPS13 PMIC which is similiar with existing S2MPS14 PMIC. S2MPS13 has the different number of regulators from S2MPS14 and RTC/Clock is the same with the S2MPS14. Signed-off-by:
Sangbeom Kim <sbkim73@samsung.com> Reviewed-by:
Lee Jones <lee.jones@linaro.org>
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Chanwoo Choi authored
This patch adds the support for S2MPS13 PMIC clock which is same with existing S2MPS14 RTC IP. But, S2MPS13 uses all of clocks (32khz_{ap|bt|cp}). Signed-off-by: -
Chanwoo Choi authored
This patch adds S2MPS13 regulator device to existing S2MPS11 device driver. The S2MPS13 has just different number of regulators from S2MPS14. The S2MPS13 regulator device includes LDO[1-40] and BUCK[1-10]. Signed-off-by:
Mark Brown <broonie@kernel.org> Reviewed-by:
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Chanwoo Choi authored
This patch adds the support for Samsung S2MPS13 PMIC device to the sec-core MFD driver. The S2MPS13 is very similar with existing S2MPS14 and includes PMIC/ RTC/CLOCK devices. Signed-off-by:
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Heiko Stuebner authored
Add the new flag to gpll and cpll on rk3188 and similar and to gpll, cpll and npll on rk3288. Signed-off-by:
Kever Yang <kever.yang@rock-chips.com> Tested-by:
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Heiko Stuebner authored
In some cases firmware brings up plls with different parameters than the ones noted in the rate table for the specific frequency. These firmware-selected parameters are worse than the tested ones in the pll rate tables but cannot be changed by a simple clk_set_rate call when the rate stays the same. Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback that checks the runtime-parameters against the matching rate table entry and adjusts them to the table-ones if necessary. If no rate table is set or the current rate does not match any rate-table entry no changes are made. Being able to limit this adjustment to specific plls is necessary to not touch the ones supplying core components like the apll and dpll supplying the armcores and dram. Signed-off-by:
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Heiko Stuebner authored
In some cases we might need to access the data of the pll mux before the actual mux gets registered - like in the following patch adding an init-callback. Therefore populate pll_mux before registering the core pll-clock. Signed-off-by:
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Heiko Stuebner authored
This adds a flag parameter to plls that allows us to create special flags to tweak the behaviour of the plls if necessary. Signed-off-by:
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Michael Turquette authored
Merge tag 'sunxi-clocks-for-3.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner Clocks additions for 3.19 A few patches that should go through the clock tree, mostly fixes, cleanups, and new clocks additions to start to support the A80.
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Michael Turquette authored
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- 23 Nov, 2014 5 commits
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Hans de Goede authored
A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk has 2 bits selecting between 3 possible parents using values of 0, 1, 2, which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in its flag. However we do not support parent 1 (an external clock), so use a table to select parent 0 or 2, which are the 2 parents we support. Note this has not been causing any issues sofar, because we start with a parent setting of parent 0, and only ever re-parent to parent 2 (for which we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set we write a value of 2 for index 1. Tested on both a cubietruck (which uses rgmii mode) as well as a cs908 (an a31s board which uses mii mode). Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. The first output will be the normal PLL6 output, and the second will be PLL6x2. This patch fixes the PLL6 N factor in the clock driver, and removes any /2 dividers in the PLL6 factors clock part. The N factor counts from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Chen-Yu Tsai authored
Currently sunxi_divs_clk_setup assumes the number of child clocks to be the same as the number of clock-output-names, and a maximum of SUNXI_DIVS_MAX_QTY child clocks. On sun6i, PLL6 only has 1 child clock, but the parent would be used as well, thereby also having it's own clock-output-names entry. This results in an extra bogus clock being registered. This patch adds an entry for the number of child clocks alongside the data structures for them. Signed-off-by:
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Chen-Yu Tsai authored
This driver does not match the hardware, which is actually compatible to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop this driver. Signed-off-by:
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Chen-Yu Tsai authored
The apb2 clocks are actually the same as apb1 clocks on the other sunxi platforms, hence compatible with "allwinner,sun4i-a10-apb1-clk". Update the dtsi to use the new unified apb1 clk. Signed-off-by:
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