- 20 Aug, 2009 40 commits
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Sebastian Andrzej Siewior authored
in case the interrupt controller was used in an earlier life then it is possible it is that some of its sources were used and are still unmask. If the (unmasked) device is active and is creating interrupts (or one interrupts was pending since the interrupts were disabled) then the boot process "ends" very soon. Once external interrupts are enabled, we land in -> do_IRQ -> call ppc_md.get_irq() -> ipic_read() gets the source number -> irq_linear_revmap(source) -> revmap[source] == NO_IRQ -> irq_find_mapping(source) returns NO_IRQ because no source is registered -> source is NO_IRQ, ppc_spurious_interrupts gets incremented, no further action. Signed-off-by:Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Julia Lawall authored
Check that the result of kmalloc/kzalloc is not NULL before dereferencing it. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression *x; identifier f; constant char *C; @@ x = \(kmalloc\|kcalloc\|kzalloc\)(...); ... when != x == NULL when != x != NULL when != (x || ...) ( kfree(x) | f(...,C,...,x,...) | *f(...,x,...) | *x->f ) // </smpl> Signed-off-by:
Julia Lawall <julia@diku.dk> Signed-off-by:
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Roel Kluin authored
cam[tlbcam_index] is checked before tlbcam_index < ARRAY_SIZE(cam) Signed-off-by:
Roel Kluin <roel.kluin@gmail.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Kumar Gala authored
Added a device tree that should be similiar to mpc8536ds.dtb except the physical addresses for all IO are above the 4G boundary. Signed-off-by:
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Kumar Gala authored
Change the top-level #address-cells and #size-cells to <2> so the mpc8536ds.dts is easier to deal with both a true 32-bit physical or 36-bit physical address space. Signed-off-by:
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Stefan Roese authored
This patch adds support for the following devices to the Kilauea defconfig file: - PPC4xx NAND controller (NDFC) - I2C RTC (Dallas DS1338) - I2C HWMON (Dallas DS1775) Signed-off-by:
Stefan Roese <sr@denx.de> Signed-off-by:
Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by:
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Stefan Roese authored
This patch adds support for the following devices to the Canyonlands defconfig file: - NOR FLASH - PPC4xx NAND controller (NDFC) - I2C RTC (M41T80) Signed-off-by:
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Stefan Roese authored
This patch adds support for the following devices to the Kilauea dts: - PPC4xx NAND controller (NDFC) - I2C RTC (Dallas DS1338) - I2C HWMON (Dallas DS1775) Additionally the partitioning of the NOR FLASH is changed. The dtb partition has been missing. Fixed in this patch. Signed-off-by:
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Stefan Roese authored
Also some whitespace cleanup in the USB device nodes. Signed-off-by:
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Stefan Roese authored
Signed-off-by:
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Kumar Gala authored
Introduced a temporary variable into our iterating over the list cpus that are threads on the same core. For some reason Ben forgot how for loops work. Signed-off-by:
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Benjamin Herrenschmidt authored
The mask used to encode the page table cache number in the batch when freeing page tables was too small for the new possible values of MMU page sizes. This increases it along with a comment explaining the constraints. Signed-off-by: -
Benjamin Herrenschmidt authored
This contains all the bits that didn't fit in previous patches :-) This includes the actual exception handlers assembly, the changes to the kernel entry, other misc bits and wiring it all up in Kconfig. Signed-off-by: -
Benjamin Herrenschmidt authored
The base TLB support didn't include support for SPARSEMEM_VMEMMAP, though we did carve out some virtual space for it, the necessary support code wasn't there. This implements it by using 16M pages for now, though the page size could easily be changed at runtime if necessary. Signed-off-by: -
Benjamin Herrenschmidt authored
This adds the TLB miss handler assembly, the low level TLB flush routines along with the necessary hook for dealing with our virtual page tables or indirect TLB entries that need to be flushes when PTE pages are freed. There is currently no support for hugetlbfs Signed-off-by: -
Benjamin Herrenschmidt authored
The definition for the global structure mmu_gathers, used by generic code, is currently defined in multiple places not including anything used by 64-bit Book3E. This changes it by moving to one place common to all processors. Signed-off-by: -
Benjamin Herrenschmidt authored
This adds various fields in the PACA that are for use specifically by Book3E processors, such as exception save areas, current pgd pointer, special exceptions kernel stacks etc... Signed-off-by: -
Benjamin Herrenschmidt authored
This adds various definitions and macros used by the exception and TLB miss handling on 64-bit BookE It also adds the definitions of the SPRGs used for various exception types Signed-off-by: -
Benjamin Herrenschmidt authored
This adds the PTE and pgtable format definitions, along with changes to the kernel memory map and other definitions related to implementing support for 64-bit Book3E. This also shields some asm-offset bits that are currently only relevant on 32-bit We also move the definition of the "linux" page size constants to the common mmu.h file and add a few sizes that are relevant to embedded processors. Signed-off-by: -
Benjamin Herrenschmidt authored
This adds various SPRs defined on 64-bit BookE, along with changes to the definition of the base MSR values to add the values needed for 64-bit Book3E. Signed-off-by: -
Benjamin Herrenschmidt authored
That patch used to just add a hook to page table flushing but pulling that string brought out a whole bunch of issues, so it now does that and more: - We now make the RCU batching of page freeing SMP only, as I believe it was intended initially. We make a few more things compile to nothing on !CONFIG_SMP - Some macros are turned into functions, though that forced me to out of line a few stuffs due to unsolvable include depenencies, however it's probably better that way anyway, it's not -that- critical code path. - 32-bit didn't call pte_free_finish() on tlb_flush() which means that it wouldn't push out the batch to RCU for delayed freeing when a bunch of page tables have been freed, they would just stay in there until the batch gets full. 64-bit BookE will use that hook to maintain the virtually linear page tables or the indirect entries in the TLB when using the HW loader. Signed-off-by: -
Benjamin Herrenschmidt authored
Those definitions are currently declared extern in the .c file where they are used, move them to a header file instead. Signed-off-by: -
Benjamin Herrenschmidt authored
Currently, a single ifdef covers SLB related bits and more generic ppc64 related bits, split this in two separate ifdef's since 64-bit BookE will need one but not the other. Signed-off-by:
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Benjamin Herrenschmidt authored
Our 64-bit hash context handling has no init function, but 64-bit Book3E will use the common mmu_context_nohash.c code which does, so define an empty inline mmu_context_init() for 64-bit server and call it from our 64-bit setup_arch() Signed-off-by:
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Benjamin Herrenschmidt authored
We need to pass down whether the page is direct or indirect and we'll need to pass the page size to _tlbil_va and _tlbivax_bcast We also add a new low level _tlbil_pid_noind() which does a TLB flush by PID but avoids flushing indirect entries if possible This implements those new prototypes but defines them with inlines or macros so that no additional arguments are actually passed on current processors. Signed-off-by: -
Benjamin Herrenschmidt authored
The way I intend to use tophys/tovirt on 64-bit BookE is different from the "trick" that we currently play for 32-bit BookE so change the condition of definition of these macros to make it so. Also, make sure we only use rfid and mtmsrd instead of rfi and mtmsr for 64-bit server processors, not all 64-bit processors. Signed-off-by:
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Benjamin Herrenschmidt authored
This adds some code to do early ioremap's using page tables instead of bolting entries in the hash table. This will be used by the upcoming 64-bits BookE port. The patch also changes the test for early vs. late ioremap to use slab_is_available() instead of our old hackish mem_init_done. Signed-off-by: -
Benjamin Herrenschmidt authored
This adds various additional bit definitions for various MMU related SPRs used on Book3E. Signed-off-by: -
Benjamin Herrenschmidt authored
This adds the opcode definitions to ppc-opcode.h for the two instructions tlbivax and tlbsrx. as defined by Book3E 2.06 Signed-off-by: -
Benjamin Herrenschmidt authored
The current "no hash" MMU context management code is written with the assumption that one CPU == one TLB. This is not the case on implementations that support HW multithreading, where several linux CPUs can share the same TLB. This adds some basic support for this to our context management and our TLB flushing code. It also cleans up the optional debugging output a bit Signed-off-by: -
Benjamin Herrenschmidt authored
enter_prom() used to save and restore registers such as CTR, XER etc.. which are volatile, or SRR0,1... which we don't care about. This removes a bunch of useless code and while at it turns an mtmsrd into an MTMSRD macro which will be useful to Book3E. Signed-off-by: -
Benjamin Herrenschmidt authored
A misplaced #endif causes more definitions than intended to be protected by #ifndef __ASSEMBLY__. This breaks upcoming 64-bit BookE support patch when using 64k pages. Signed-off-by: -
Benjamin Herrenschmidt authored
The truncate syscall has a signed long parameter, so when using a 32- bit userspace with a 64-bit kernel the argument is zero-extended instead of sign-extended. Adding the compat_sys_truncate function fixes the issue. This was noticed during an LSB truncate test failure. The test was checking for the correct error number set when truncate is called with a length of -1. The test can be found at: http://bzr.linuxfoundation.org/lsb/devel/runtime-test?cmd=inventory;rev=stewb%40linux-foundation.org-20090626205411-sfb23cc0tjj7jzgm;path=modules/vsx-pcts/tset/POSIX.os/files/truncate/ BenH: Added compat_sys_ftruncate() as well, same issue. Signed-off-by:
Chase Douglas <cndougla@linux.vnet.ibm.com> Signed-off-by:
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Lucian Adrian Grijincu authored
dtc was moved in 9fffb55f from arch/powerpc/boot/ to scripts/dtc/ This patch updates the wrapper script to point to the new location of dtc. Signed-off-by:
Lucian Adrian Grijincu <lgrijincu@ixiacom.com> Signed-off-by:
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Frans Pop authored
Signed-off-by:
Frans Pop <elendil@planet.nl> Acked-by:
Sam Ravnborg <sam@ravnborg.org> Signed-off-by:
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Benjamin Herrenschmidt authored
This change the SPRG used to store the PACA on ppc64 from SPRG3 to SPRG1. SPRG3 is user readable on most processors and we want to use it for other things. We change the scratch SPRG used by exception vectors from SRPG1 to SPRG2. Signed-off-by: -
Benjamin Herrenschmidt authored
The code for setting up the IPIs for SMP PowerSurge marchines bitrot, it needs to properly map the HW interrupt number Signed-off-by: -
Benjamin Herrenschmidt authored
The current definitions set ranges and defaults for 32 and 64-bit only using "PPC_STD_MMU" which means hash based MMU. This uselessly restrict the usefulness for the upcoming 64-bit BookE port, but more than that, it's broken on 32-bit since the only 32-bit platform supporting multiple page sizes currently is 44x which does -not- have PPC_STD_MMU_32 set. This fixes it by using PPC64 and PPC32 instead. Signed-off-by: -
roel kluin authored
Replace strncpy() and explicit null-termination by strlcpy() Signed-off-by:
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Benjamin Herrenschmidt authored
The STAB code used on Power3 and RS/64 uses a second scratch SPRG to save a GPR in order to decide whether to go to do_stab_bolted_* or to handle a normal data access exception. This prevents our scheme of freeing SPRG3 which is user visible for user uses since we cannot use SPRG0 which, on RS/64, seems to be read-only for supervisor mode (like POWER4). This reworks the STAB exception entry to use the PACA as temporary storage instead. Signed-off-by:
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