- 13 Aug, 2015 5 commits
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Wu Fengguang authored
drivers/crypto/qat/qat_common/adf_sriov.c:258:1-4: WARNING: end returns can be simpified and declaration on line 212 can be dropped Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci CC: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Tadeusz Struk authored
Reported-by:
Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by:
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Chen-Yu Tsai authored
A31/A31s have the same "Security System" crypto engine as A10/A20, but with a separate reset control. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Chen-Yu Tsai authored
On sun6i and later platforms, the reset control is split out of the clock gates. Add support for an optional reset control. Signed-off-by:
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Chen-Yu Tsai authored
Later Allwinner SoCs split out the reset controls for individual modules out of the clock gate controls. The "Security System" crypto engine is no different. Signed-off-by:
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- 11 Aug, 2015 2 commits
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Tadeusz Struk authored
When both PF and VF drivers are build in linker complains about multiple definition of adf_isr_resource_[alloc/free] functions. Reported-by:
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Paulo Flabiano Smorigo authored
Signed-off-by:
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- 10 Aug, 2015 26 commits
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Leonidas Da Silva Barbosa authored
CTR hardware implementation does not match with kernel spec causing a counter bug where just low 8 bytes are used for counter, when should be all 16bytes. Since we already have other counter modes working according with specs not worth to keep CTR itself on NX. Signed-off-by:
Leonidas S. Barbosa <leosilva@linux.vnet.ibm.com> Signed-off-by:
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Leonidas Da Silva Barbosa authored
Marcelo and Fin are no long IBMers, thus no longer NX maintainers. Updating with the new names. Adding VMX crypto maintainers. Signed-off-by:
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Tadeusz Struk authored
The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with QuickAssist Technology is prematurely terminated in hardware. Workaround the issue by hard-coding the known expected next capability pointer and saving the PCIE cap into internal buffer. Patch generated against cryptodev-2.6 Signed-off-by:
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Tadeusz Struk authored
Some VF drivers need FW const table, so the PF driver needs to load it. Signed-off-by:
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Tadeusz Struk authored
Add code specific for the dh895xcc virtual function. Signed-off-by:
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Tadeusz Struk authored
Add code that enables SRIOV on dh895xcc devices. Signed-off-by:
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Tadeusz Struk authored
Adf admin and HW arbiter function can be used by dh895xcc specific code well as the new dh895xccvf and future devices so moving them to qat_common so that they can be shared. Signed-off-by:
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Herbert Xu authored
This patch converts authencesn to the new AEAD interface. Signed-off-by: -
Brian Norris authored
The HTML output works a little nicer that way. Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
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Aaron Sierra authored
The probe error path for this driver, for all intents and purposes, is the talitos_remove() function due to the common "goto err_out". Without this patch applied, talitos_remove() will panic under these two conditions: 1. If the RNG device hasn't been registered via talitos_register_rng() prior to entry into talitos_remove(), then the attempt to unregister the RNG "device" will cause a panic. 2. If the priv->chan array has not been allocated prior to entry into talitos_remove(), then the per-channel FIFO cleanup will panic because of the dereference of that NULL "array". Both of the above scenarios occur if talitos_probe_irq() fails. This patch resolves issue #1 by introducing a boolean to mask the hwrng_unregister() call in talitos_unregister_rng() if RNG device registration was unsuccessful. It resolves issue #2 by checking that priv->chan is not NULL in the per-channel FIFO cleanup for loop. Signed-off-by:
Aaron Sierra <asierra@xes-inc.com> Signed-off-by:
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Victoria Milhoan authored
Select CAAM for i.MX6 devices. Signed-off-by:
Victoria Milhoan <vicki.milhoan@freescale.com> Tested-by:
Horia Geantă <horia.geanta@freescale.com> Signed-off-by:
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Victoria Milhoan authored
Register only algorithms supported by CAAM hardware, using the CHA version and instantiation registers to identify hardware capabilities. Signed-off-by:
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Steve Cornelius authored
Allow CAAM to be selected in the kernel for Freescale i.MX devices if ARCH_MXC is enabled. Signed-off-by:
Steve Cornelius <steve.cornelius@freescale.com> Signed-off-by:
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Victoria Milhoan authored
Add CAAM device node to the i.MX6SX device tree. Signed-off-by:
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Victoria Milhoan authored
Add CAAM device node to the i.MX6 device tree. Signed-off-by:
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Victoria Milhoan authored
Add CAAM clock support to the i.MX6 clocking infrastructure. Signed-off-by:
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Victoria Milhoan authored
The clocks and clock-names properties describe input clocks that may be required for enablement of CAAM. Signed-off-by:
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Victoria Milhoan authored
Avoid moving the head of the scatterlist entry by using temporary pointers to walk the scatterlist. Signed-off-by:
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Victoria Milhoan authored
This change fixes: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 456 at lib/dma-debug.c:1103 check_unmap+0x438/0x958() caam_jr 2101000.jr0: DMA-API: device driver frees DMA memory with different size [device address=0x000000003a241080] [map ] Modules linked in: tcrypt(+) CPU: 0 PID: 456 Comm: insmod Not tainted 4.1.0-248766-gf823586-dirty #82 Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [<80015e0c>] (unwind_backtrace) from [<80012764>] (show_stack+0x10/0x14) [<80012764>] (show_stack) from [<806df8e8>] (dump_stack+0x84/0xc4) [<806df8e8>] (dump_stack) from [<800266fc>] (warn_slowpath_common+0x84/0xb4) [<800266fc>] (warn_slowpath_common) from [<8002675c>] (warn_slowpath_fmt+0x30/0x40) [<8002675c>] (warn_slowpath_fmt) from [<802c7db8>] (check_unmap+0x438/0x958) [<802c7db8>] (check_unmap) from [<802c835c>] (debug_dma_unmap_page+0x84/0x8c) [<802c835c>] (debug_dma_unmap_page) from [<804d3b94>] (ahash_update_ctx+0xb08/0xec4) [<804d3b94>] (ahash_update_ctx) from [<7f002984>] (test_ahash_pnum.isra.9.constprop.19+0x2b8/0x514 [tcrypt]) [<7f002984>] (test_ahash_pnum.isra.9.constprop.19 [tcrypt]) from [<7f005998>] (do_test+0x2db8/0x37cc [tcrypt]) [<7f005998>] (do_test [tcrypt]) from [<7f00b050>] (tcrypt_mod_init+0x50/0x9c [tcrypt]) [<7f00b050>] (tcrypt_mod_init [tcrypt]) from [<80009730>] (do_one_initcall+0x8c/0x1d4) [<80009730>] (do_one_initcall) from [<806dda4c>] (do_init_module+0x5c/0x1a8) [<806dda4c>] (do_init_module) from [<80085308>] (load_module+0x17e0/0x1da0) [<80085308>] (load_module) from [<80085998>] (SyS_init_module+0xd0/0x120) [<80085998>] (SyS_init_module) from [<8000f4c0>] (ret_fast_syscall+0x0/0x3c) ---[ end trace 60807cfb6521c79f ]--- Signed-off-by:
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Victoria Milhoan authored
Since fields must be ORed in to operate correctly using any order of operations, changed allocations of the combination of extended descriptor structs + hardware scatterlists to use kzalloc() instead of kmalloc(), so as to ensure that residue data would not be ORed in with the correct data. Signed-off-by:
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Victoria Milhoan authored
Modify the Scatter-Gather entry definitions for the Freescale CAAM driver to include support for both 64- and 32-bit DMA pointers. Signed-off-by:
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Victoria Milhoan authored
ARM-based systems may disable clocking to the CAAM device on the Freescale i.MX platform for power management purposes. This patch enables the required clocks when the CAAM module is initialized and disables the required clocks when the CAAM module is shut down. Signed-off-by:
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Victoria Milhoan authored
Add set/clear 32-bit primitives for compatibility with ARM devices since the primitives were previously only defined for the Power architecture. Signed-off-by:
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Victoria Milhoan authored
Freescale i.MX6 ARM platforms do not support hardware cache coherency. This patch adds cache coherency support to the CAAM driver. Signed-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Herbert Xu authored
Merge the crypto tree to pull in the authencesn fix.
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Herbert Xu authored
The ESP code has been updated to generate a completely linear AD SG list. This unfortunately broke authencesn which expects the AD to be divided into at least three parts. This patch fixes it to cope with the new format. Later we will fix it properly to accept arbitrary input and not rely on the input being linear as part of the AEAD conversion. Fixes: 7021b2e1 ("esp4: Switch to new AEAD interface") Signed-off-by:
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- 05 Aug, 2015 1 commit
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Herbert Xu authored
CRYPTO_AUTHENC needs to depend on CRYPTO_NULL as authenc uses null for copying. Reported-by:
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- 04 Aug, 2015 6 commits
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Herbert Xu authored
Now that all implementations of authenc have been converted we can reenable the tests. Signed-off-by: -
Herbert Xu authored
This patch converts talitos to the new AEAD interface. IV generation has been removed since it's equivalent to a software implementation. Signed-off-by: -
Herbert Xu authored
This patch converts qat to the new AEAD interface. IV generation has been removed since it's equivalent to a software implementation. Signed-off-by:
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Herbert Xu authored
This patch converts picoxcell to the new AEAD interface. IV generation has been removed since it's equivalent to a software implementation. As picoxcell cannot handle SG lists longer than 16 elements, this patch has made the software fallback mandatory. If an SG list comes in that exceeds the limit, we will simply use the fallback. Signed-off-by: -
Herbert Xu authored
This patch converts ixp4xx to the new AEAD interface. IV generation has been removed since it's a purely software implementation. Signed-off-by: -
Herbert Xu authored
This patch converts the authenc implementations in caam to the new AEAD interface. The biggest change is that seqiv no longer generates a random IV. Instead the IPsec sequence number is used as the IV. Signed-off-by:
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