- 24 Nov, 2011 40 commits
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Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p2041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level Signed-off-by:Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & * etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1023-IP..." from compatibles for standard blocks * Removed incorrect power/pmc node, there are no etsec on P1023 Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Updated spi node to new espi binding specification * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1022-IP..." from compatibles for standard blocks * Fixed bug in local bus range node for CS2, was maping to 0x0 0x0xffa00000 instead of 0xf 0xffa00000 * Fixed localbus reg property should have been 0xf 0xffe05000 Signed-off-by:
Timur Tabi <timur@freescale.com>
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Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1021-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1010-IP..." from compatibles for standard blocks * PCI interrupt map - wrong IRQs for PCI-0 controller * SDHC interrupt sense was wrong Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Dropping "fsl,mpc8569-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Dropping "fsl,mpc8568-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Moved mdio nodes up one level instead of under tsec nodes * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Added MPIC / PCIe msi node * Dropping "fsl,mpc8548-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: -
Kumar Gala authored
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) * and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8536 SoC template [ marked as MPC8572 compatiable to get errata handling that applies ] * Added missing cache-line-size & cache-size properties missing from L2-cache node * Added IP level IEEE 1588 / ptp timer node Signed-off-by: -
Kumar Gala authored
Introduce some common components that we can utilize to build up the various PQ3/85xx device trees. Signed-off-by: -
Kumar Gala authored
* set interrupt-parent at root so its not duplicate in every node * Add mpic timers * Move to 4-prop cells for mpic timer Signed-off-by: -
Kumar Gala authored
All eTSEC2 controllers support waking on magic packet so fixup device tree to report that. Signed-off-by: -
Kumar Gala authored
Signed-off-by: -
Kumar Gala authored
The SPI node is out of date with regards to the binding for fsl-espi and driver support. Signed-off-by: -
Kumar Gala authored
* Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts Signed-off-by: -
Kumar Gala authored
If we include the p1020rdb.dts instead of p1020si.dts we greatly reduce duplication and maintenance. We can just list which devices are disabled for the given core and mpic protected sources. Signed-off-by: -
Kai Jiang authored
Update of_platform_bus_probe() RapidIO node to be compitable with new RapidIO dts compatible property. Signed-off-by:
Kai Jiang <Kai.Jiang@freescale.com> Acked-by:
Alexandre Bounine <alexandre.bounine@idt.com> Signed-off-by:
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Liu Gang authored
Usually, freescale rapidio endpoint can support one or two 1x or 4X LP-Serial link interfaces, and rapidio message transactions can be implemented by two message units. This adds the support of two rapidio ports and initializes message unit 0 and message unit 1. And these ports and message units can work simultaneously. Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Jin Qing <b24347@freescale.com> Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Acked-by:
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Liu Gang authored
The Freescale PowerPC RapidIO controller consists of a RapidIO endpoint and a RapidIO message unit(RMU). Or use RapidIO message manager(RMan) to replace the RMU in DPAA architecture. Therefore, we should split the code into two function modules according to the hardware architecture. Add new struct for RMU module, and new initialization function to set up RMU module. This policy is very conducive to adding new module like RMan, or adding multi-ports or message units support. Signed-off-by:
Lian Minghuan <Minghuan.Lian@freescale.com> Signed-off-by:
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Liu Gang authored
This document is created for powerpc rapidio and rmu nodes in dts file. These nodes can support two rapidio ports and message units. In addition, It explicates the properties and gives examples about rapidio and rmu nodes. Signed-off-by:
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Julia Lawall authored
At this point, ehv_pic has been allocated but not stored anywhere, so it should be freed before leaving the function. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @exists@ local idexpression x; statement S,S1; expression E; identifier fl; expression *ptr != NULL; @@ x = \(kmalloc\|kzalloc\|kcalloc\)(...); ... if (x == NULL) S <... when != x when != if (...) { <+...kfree(x)...+> } when any when != true x == NULL x->fl ...> ( if (x == NULL) S1 | if (...) { ... when != x when forall ( return \(0\|<+...x...+>\|ptr\); | * return ...; ) } ) // </smpl> Signed-off-by:
Julia Lawall <julia@diku.dk> Acked-by:
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Alexandre Rusev authored
If Freescale LBC driver fails to initialise itself from device tree, then internal structure is freed only but not NULL-fied. As result functions fsl_lbc_find() after checking the structure is not NULL are trying to access device registers. Signed-off-by:
Alexandre Rusev <arusev@dev.rtsoft.ru> Signed-off-by:
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Shaohui Xie authored
compatible in dts has been changed, so the driver needs to be updated accordingly. Signed-off-by:
Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Joakim Tjernlund authored
QE_General4 should only round up the divisor iff divisor is > 3. Rounding up lower divisors makes the error too big, causing USB on MPC832x to fail. Signed-off-by:
Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by:
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Kumar Gala authored
arch/powerpc/platforms/85xx/p3060_qds.c: In function '__machine_initcall_p3060_qds_declare_of_platform_devices': arch/powerpc/platforms/85xx/p3060_qds.c:73:1: error: implicit declaration of function 'declare_of_platform_devices' declare_of_platform_devices should have been corenet_ds_publish_devices. Signed-off-by: -
Paul Bolle authored
The driver for the Freescale P3060 QDS got added by commit 96cc017c ("[...] Add support for P3060QDS board"). Its Kconfig entry selects MPC8xxx_GPIO. But at the time that driver got added MPC8xxx_GPIO was already renamed to GPIO_MPC8XXX, by commit c68308dd ("gpio: move mpc8xxx/512x gpio driver to drivers/gpio"). So make this driver select GPIO_MPC8XXX. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Acked-by:
Wolfram Sang <w.sang@pengutronix.de> Signed-off-by:
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Roy Zang authored
P1023 external IRQ[4:6, 11] are not pin out, but the interrupts are utilized by the PCIe controllers. As they are not exposed as pins we need to set them as active-high (internal to the SoC these interrupts are pulled down). IRQs[0:3,7:10] are pulled up on the board so we have them set as active-low. Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
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Linus Torvalds authored
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git://github.com/rustyrussell/linuxLinus Torvalds authored
* git://github.com/rustyrussell/linux: virtio-pci: make reset operation safer virtio-mmio: Correct the name of the guest features selector virtio: add HAS_IOMEM dependency to MMIO platform bus driver
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Michael S. Tsirkin authored
virtio pci device reset actually just does an I/O write, which in PCI is really posted, that is it can complete on CPU before the device has received it. Further, interrupts might have been pending on another CPU, so device callback might get invoked after reset. This conflicts with how drivers use reset, which is typically: reset unregister a callback running after reset completed can race with unregister, potentially leading to use after free bugs. Fix by flushing out the write, and flushing pending interrupts. This assumes that device is never reset from its vq/config callbacks, or in parallel with being added/removed, document this assumption. Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
Rusty Russell <rusty@rustcorp.com.au>
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Sasha Levin authored
Guest features selector spelling mistake. Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: virtualization@lists.linux-foundation.org Signed-off-by:
Sasha Levin <levinsasha928@gmail.com> Signed-off-by:
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