- 01 Mar, 2010 40 commits
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Gleb Natapov authored
For some instructions CPU behaves differently for real-mode and virtual 8086. Let emulator know which mode cpu is in, so it will not poke into vcpu state directly. Signed-off-by:
Gleb Natapov <gleb@redhat.com> Cc: stable@kernel.org Signed-off-by:
Avi Kivity <avi@redhat.com>
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Gleb Natapov authored
Use groups mechanism to decode 0F C7 instructions. Signed-off-by:
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Gleb Natapov authored
Use groups mechanism to decode 0F BA instructions. Signed-off-by:
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Michael S. Tsirkin authored
wqh is unused, so we do not need to store it in irqfd anymore Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
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Liu Yu authored
Old method prematurely sets ESR and DEAR. Move this part after we decide to inject interrupt, which is more like hardware behave. Signed-off-by:
Liu Yu <yu.liu@freescale.com> Acked-by:
Hollis Blanchard <hollis@penguinppc.org> Acked-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Wei Yongjun authored
If KVM_CREATE_IRQCHIP fail due to kvm_setup_default_irq_routing(), ioapic device is not destroyed and kvm->arch.vioapic is not set to NULL, this may cause KVM_GET_IRQCHIP and KVM_SET_IRQCHIP access to unexcepted memory. Signed-off-by:
Wei Yongjun <yjwei@cn.fujitsu.com> Signed-off-by:
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Wei Yongjun authored
If we fail to init ioapic device or the fail to setup the default irq routing, the device register by kvm_create_pic() and kvm_ioapic_init() remain unregister. This patch fixed to do this. Signed-off-by:
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Wei Yongjun authored
kvm->arch.vioapic should be NULL in case of kvm_ioapic_init() failure due to cannot register io dev. Signed-off-by:
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Wei Yongjun authored
If fail to create pit, we should unregister kvm irq notifier which register in kvm_create_pit(). Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
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Sheng Yang authored
Following the new SDM. Now the bit is named "Ignore PAT memory type". Signed-off-by:
Sheng Yang <sheng@linux.intel.com> Signed-off-by:
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Avi Kivity authored
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Jochen Maes authored
Fixed 2 codestyle issues in virt/kvm/coalesced_mmio.c Signed-off-by:
Jochen Maes <jochen.maes@sejo.be> Signed-off-by:
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Takuya Yoshikawa authored
kvm_emulate_pio() and complete_pio() both read out the RAX register value and copy it to a place into which the value read out from the port will be copied later. This patch removes this redundancy. /*** snippet from arch/x86/kvm/x86.c ***/ int complete_pio(struct kvm_vcpu *vcpu) { ... if (!io->string) { if (io->in) { val = kvm_register_read(vcpu, VCPU_REGS_RAX); memcpy(&val, vcpu->arch.pio_data, io->size); kvm_register_write(vcpu, VCPU_REGS_RAX, val); } ... Signed-off-by:Takuya Yoshikawa <yoshikawa.takuya@oss.ntt.co.jp> Signed-off-by:
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Rik van Riel authored
Currently KVM pretends that pages with EPT mappings never got accessed. This has some side effects in the VM, like swapping out actively used guest pages and needlessly breaking up actively used hugepages. We can avoid those very costly side effects by emulating the accessed bit for EPT PTEs, which should only be slightly costly because pages pass through page_referenced infrequently. TLB flushing is taken care of by kvm_mmu_notifier_clear_flush_young(). This seems to help prevent KVM guests from being swapped out when they should not on my system. Signed-off-by:
Rik van Riel <riel@redhat.com> Signed-off-by:
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Joerg Roedel authored
This patch introduces a generic function to find out the host page size for a given gfn. This function is needed by the kvm iommu code. This patch also simplifies the x86 host_mapping_level function. Signed-off-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
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Julia Lawall authored
msr was tested above, so the second test is not needed. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r@ expression *x; expression e; identifier l; @@ if (x == NULL || ...) { ... when forall return ...; } ... when != goto l; when != x = e when != &x *x == NULL // </smpl> Signed-off-by:
Julia Lawall <julia@diku.dk> Signed-off-by:
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Joe Perches authored
String constants that are continued on subsequent lines with \ are not good. Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Avi Kivity authored
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Takuya Yoshikawa authored
This patch fixes kvm_fix_hypercall() to propagate X86EMUL_* info generated by emulator_write_emulated() to its callers: suggested by Marcelo. The effect of this is x86_emulate_insn() will begin to handle the page faults which occur in emulator_write_emulated(): this should be OK because emulator_write_emulated_onepage() always injects page fault when emulator_write_emulated() returns X86EMUL_PROPAGATE_FAULT. Signed-off-by:
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Takuya Yoshikawa authored
This patch fixes load_guest_segment_descriptor() to return X86EMUL_PROPAGATE_FAULT when it tries to access the descriptor table beyond the limit of it: suggested by Marcelo. I have checked current callers of this helper function, - kvm_load_segment_descriptor() - kvm_task_switch() and confirmed that this patch will change nothing in the upper layers if we do not change the handling of this return value from load_guest_segment_descriptor(). Next step: Although fixing the kvm_task_switch() to handle the propagated faults properly seems difficult, and maybe not worth it because TSS is not used commonly these days, we can fix kvm_load_segment_descriptor(). By doing so, the injected #GP becomes possible to be handled by the guest. The only problem for this is how to differentiate this fault from the page faults generated by kvm_read_guest_virt(). We may have to split this function to achive this goal. Signed-off-by:
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Zhai, Edwin authored
Enable optional parameter (default 0) - PCI segment (or domain) besides BDF, when assigning PCI device to guest. Signed-off-by:
Zhai Edwin <edwin.zhai@intel.com> Acked-by:
Chris Wright <chrisw@sous-sol.org> Signed-off-by:
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Gui Jianfeng authored
flexpriority_enabled implies cpu_has_vmx_virtualize_apic_accesses() returning true, so we don't need this check here. Signed-off-by:
Gui Jianfeng <guijianfeng@cn.fujitsu.com> Signed-off-by:
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Avi Kivity authored
Record failed msrs reads and writes, and the fact that they failed as well. Signed-off-by:
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Avi Kivity authored
- data is 64 bits wide, not unsigned long - rw is confusingly named Signed-off-by:
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Gleb Natapov authored
On HW task switch newly loaded segments should me marked as accessed. Reported-by:
Lorenzo Martignoni <martignlo@gmail.com> Signed-off-by:
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Avi Kivity authored
When cr0.mp is clear, the guest doesn't expect a #NM in response to a WAIT instruction. Because we always keep cr0.mp set, it will get a #NM, and potentially be confused. Fix by keeping cr0.mp set only when the fpu is inactive, and passing it through when inactive. Reported-by:
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Liu Yu authored
commit 55fb1027c1cf9797dbdeab48180da530e81b1c39 doesn't update tlbcfg correctly. Fix it. And since guest OS likes 'fixed' hardware, initialize tlbcfg everytime when guest access is useless. So move this part to init code. Signed-off-by:
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Liu Yu authored
commit 513579e3 change the way we emulate PVR/PIR, which left PVR/PIR uninitialized on E500, and make guest puzzled. Signed-off-by:
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Liu Yu authored
Latest kernel start to access l1csr0 to contron L1. We just tell guest no operation is on going. Signed-off-by:
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Wei Yongjun authored
If we fail to alloc page for vcpu->arch.mmu.pae_root, call to free_mmu_pages() is unnecessary, which just do free the page malloc for vcpu->arch.mmu.pae_root. Signed-off-by:
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Avi Kivity authored
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Avi Kivity authored
'mask' is always a constant, so we can check whether it includes a bit that might be owned by the guest very cheaply, and avoid the decache call. Saves a few hundred bytes of module text. Signed-off-by:
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Avi Kivity authored
None of the other registers have the shadow_ prefix. Signed-off-by:
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Avi Kivity authored
They have more general scope than the mmu. Signed-off-by:
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Avi Kivity authored
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Avi Kivity authored
Assume that if the guest executes clts, it knows what it's doing, and load the guest fpu to prevent an #NM exception. Signed-off-by:
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Avi Kivity authored
Not used anymore. Signed-off-by:
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Avi Kivity authored
This allows accessing the guest fpu from the instruction emulator, as well as being symmetric with kvm_put_guest_fpu(). Signed-off-by:
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Gleb Natapov authored
Move to/from Control Registers chapter of Intel SDM says. "Reserved bits in CR0 remain clear after any load of those registers; attempts to set them have no impact". Control Register chapter says "Bits 63:32 of CR0 are reserved and must be written with zeros. Writing a nonzero value to any of the upper 32 bits results in a general-protection exception, #GP(0)." This patch tries to implement this twisted logic. Signed-off-by:
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Sheng Yang authored
The commit 0953ca73 "KVM: Simplify coalesced mmio initialization" allocate kvm_coalesced_mmio_ring in the kvm_coalesced_mmio_init(), but didn't discard the original allocation... Signed-off-by:
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