- 23 Jun, 2015 5 commits
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Silvan Wicki authored
Checks if the cdiv value is in between min (0x2) and max (0xFFFE) supported values by the bcm2835. If not, it returns -ENODEV. See page 33/34 of BCM2835-ARM-Peripherals.pdf for the DIV register. https://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdfSigned-off-by:
Silvan Wicki <linux_wi@tinag.ch> [wsa: resolved a merge conflict] Signed-off-by:
Wolfram Sang <wsa@the-dreams.de>
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Wolfram Sang authored
wait_event_timeout returns long, not int. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Wolfram Sang authored
5 seconds is a very large timeout, and it is hardcoded. Use the default timeout from 'struct adapter' which is 1 second. It can also be modified from userspace for specific workloads via i2c-dev. Signed-off-by:
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Wolfram Sang authored
wait_event_timeout returns long, not int. Signed-off-by:
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Wolfram Sang authored
5 seconds is a very large timeout, and it is hardcoded. Use the default timeout from 'struct adapter' which is 1 second. It can also be modified from userspace for specific workloads via i2c-dev. Signed-off-by:
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- 21 Jun, 2015 3 commits
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Mika Westerberg authored
The driver calls pm_runtime_put() right before pm_runtime_disable() in its ->remove() hook to make sure clock is gated etc. However, it turns out that pm_runtime_put() only calls ->idle() hook without actually suspending anything. The following pm_runtime_disable() will prevent the driver from suspending thus leaving it "active". It is better to suspend the device synchronously to make sure it is actually suspended before disabling runtime PM from it. While there, undo call to pm_runtime_use_autosuspend(). Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Wolfram Sang authored
payload_size is a 12 bit field in the HW register, so add a limit for this size. That way we gracefully reject the message beforehand instead of generating an OOPS while transferring. Verified using some older Tegra2 documentation and a more recent Jetson TK1 board. Signed-off-by:
Alexander Sverdlin <alexander.sverdlin@nokia.com>
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Wolfram Sang authored
This HW cannot send 0-byte-length messages and the driver discards them. So, we should not advertise SMBUS_QUICK. Signed-off-by:
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- 17 Jun, 2015 8 commits
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Nicholas Mc Guire authored
'commit 2637e5fd ("i2c: octeon: Fix i2c fail problem when a process is terminated by a signal")' removed the wait_event_interruptible_timeout to prevent half/mixed i2c messages from being sent/recievd but forgot to drop the signal handling case in the return handling. This just removes this dead code. While at it the return variable is adjusted to the type expected. Signed-off-by:
Nicholas Mc Guire <hofrat@osadl.org> Reviewed-by:
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Alexander Sverdlin authored
There are several cases where current clock configuration algorithm produces not optimal results: - truncation in "clk" calculation leads to the fact that actual BUS frequency will be always higher than spec except two exact module frequences 8MHz and 12MHz in the whole 7-12MHz range of permitted frequences - driver configures SCL HIGH to LOW ratio always 1 to 1 and this doesn't work well in 400kHz case, namely minimum time of LOW state (according to I2C Spec 2.1) 1.3us will not be fulfilled. HIGH to LOW ratio 1 to 2 would be more approriate here. Signed-off-by:
Michael Lawnick <michael.lawnick@nokia.com> Signed-off-by:
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Alexander Sverdlin authored
pca9541 and pca954x are calling master_xfer() of the parent adapter directly thus bypassing the quirks checks of the adapter. Use __i2c_transfer() instead. Signed-off-by:
Łukasz Gemborowski <lukasz.gemborowski@nokia.com> Acked-by:
Jisheng Zhang <jszhang@marvell.com> Signed-off-by:
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Alexander Sverdlin authored
Newly introduced quirks infrastructure doesn't work for the devices behind MUXes because MUX's master_xfer() calls parent's master_xfer() directly without checking the quirks. Instead of duplicating check code in MUX just call __i2c_transfer() instead. This has a side effect on tracing (messages will appear on both MUX bus and parent bus), but maybe that's not bad at the end. Signed-off-by:
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Alexander Sverdlin authored
Inherit parent adapter quirks in MUX in case the devices on the multiplexed buses are interested in the adapter limitations. Signed-off-by:
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Silvan Wicki authored
The datasheet mentions on page 31 that the bits 10-31 must be read as don't care and written as 0. https://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf We cannot guarantee that we read bits 10-31 as always 0 (because the datasheet says read as don't care). We clear the bits with a bitmask to prevent writing back unknown data at the reserved bits. Signed-off-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
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Wolfram Sang authored
This is now done in the I2C driver. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Wolfram Sang authored
This used to be in platform init code. We want it to do in the driver now. This is basically a code move and a new compatible added. Signed-off-by:
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- 11 Jun, 2015 1 commit
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Cyrille Pitchen authored
buf_len is a size_t, so unsigned, but was tested with '<= 0'. Reported-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
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- 10 Jun, 2015 10 commits
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Feng Kan authored
Fix section mismatch error during kernel build for xgene_slimpro_i2c_probe function. It was incorrectly defined with __init declaration. Signed-off-by:
Feng Kan <fkan@apm.com> Signed-off-by:
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Alexander Sverdlin authored
Sending a message to own address locks the controller up in very bizarre state, it behaves as slave even if MDR register clearly states master. The controller remains in this state until reset. To avoid unnecessary timeouts simply avoid sending to own address. The controller cannot do this any way. Also, do not enable AAS IRQ, as the slave mode is not supported by the driver and the only possibility to trigger this IRQ is to send to own address. Signed-off-by:
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Alexander Sverdlin authored
There are several problems in the function: - "to_cnt" variable does nothing - schedule_timeout() call without setting current state does nothing - "allow_sleep" parameter is not really used Refactor the function so that it really tries to wait. In case of timeout try to recover the bus. Signed-off-by:
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Kamal Dasu authored
Adding support for i2c controller driver for Broadcom settop SoCs. Signed-off-by:
Kamal Dasu <kdasu.kdev@gmail.com> [wsa: removed superfluous owner in platform_driver] Signed-off-by:
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Cyrille Pitchen authored
When FIFOs are available and enabled, the driver now configures the Atmel eXtended DMA Controller to perform word accesses instead of byte accesses when possible. The actual access width depends on the size of the buffer to transmit. To enable FIFO support the "atmel,fifo-size" property must be set properly in the I2C controller node of the device tree. Signed-off-by:
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Cyrille Pitchen authored
The probe() function now prints the hardware version of the I2C controller. Signed-off-by:
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Cyrille Pitchen authored
The alternative command mode was introduced to simplify the transmission of STOP conditions and to solve timing and latency issues around them. This mode relies on a new register, the Alternative Command Register, which must be set at the same time as the Master Mode Register. This new register was designed to allow simple setup of basic combined transactions built from up to two unitary transactions. Indeed, the ACR is split into two areas, which describe one unitary transaction each. Each area is filled with Data Length 8bit counter, a Direction and a PEC Request bit. The PEC bit is only used in SMBus mode and is not supported by this driver yet. Also when using alternative command mode, the MREAD bit from the Master Mode Register is ignored. Instead the Direction bits from ACR are used to setup the direction, read or write, of each unitary transaction. Finally the 8bit counters must filled with the data length of their respective transaction. Then if only one transaction is to be used, the data length of the second one must be set to zero. At the moment, this driver uses only the first transaction. In addition to MMR and ACR, the Control Register also need to be written to enable the alternative command mode. That's the purpose of its ACMEN bit, which stands for Alternative Command Mode Enable. Note that the alternative command mode is compatible with the use of the Internal Address Register. So combined transactions for eeprom read are actually implemented with the Internal Address Register. This register is written with up to 3 bytes, which are the internal address sent to the slave through the first write transaction. Then the first area of the ACR describe the write transaction to follow, which carries the data to be read from the eeprom. The second area of the ACR is not used so its Data Length 8bit counter is cleared. For each byte sent or received by the device, the Data Length 8bit counter is decremented. When it reaches 0, a STOP condition is automatically sent. Signed-off-by:
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Cyrille Pitchen authored
add a new value "atmel,sama5d2-i2c" for the "compatible" property. add a new optional property "atmel,fifo-size" to enable FIFO support when available. add missing optional properties "dmas" and "dma-names". Signed-off-by:
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Cyrille Pitchen authored
This patch just fixes typo before applying later patches which will use register bits with index above 16. Signed-off-by:
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Cyrille Pitchen authored
For TX transactions, the TXCOMP bit in the Status Register is cleared when the first data is written into the Transmit Holding Register. In the lines from at91_do_twi_transfer(): at91_twi_write_data_dma(dev); at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); the TXCOMP interrupt may be enabled before the DMA controller has actually started to write into the THR. In such a case, the TXCOMP bit is still set into the Status Register so the interrupt is triggered immediately. The driver understands that a transaction completion has occurred but this transaction hasn't started yet. Hence the TXCOMP interrupt is no longer enabled by at91_do_twi_transfer() but instead by at91_twi_write_data_dma_callback(). Also, the TXCOMP bit in the Status Register in not a clear on read flag but a snapshot of the transmission state at the time the Status Register is read. When a NACK error is dectected by the I2C controller, the TXCOMP, NACK and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP interrupt is triggered at the same time. Also setting the TXRDY to 1 triggers the DMA controller to write the next data into the THR. Such a write resets the TXCOMP bit to 0 in the SR. So depending on when the interrupt handler reads the SR, it may fail to detect the NACK error if it relies on the TXCOMP bit. The NACK bit and its interrupt should be used instead. For RX transactions, the TXCOMP bit in the Status Register is cleared when the START bit is set into the Control Register. However to unify the management of the TXCOMP bit when the DMA controller is used, the TXCOMP interrupt is now enabled by the DMA callbacks for both TX and RX transfers. Signed-off-by:
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- 02 Jun, 2015 4 commits
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Ray Jui authored
Add suspend/resume support to the Broadcom iProc I2C driver Signed-off-by:
Ray Jui <rjui@broadcom.com> Reviewed-by:
Scott Branden <sbranden@broadcom.com> Signed-off-by:
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Jisheng Zhang authored
Commit 1fc2fe20 ("i2c: designware: Add runtime PM hooks") adds runtime pm support using the same ops for system pm and runtime pm. When suspend to ram, the i2c host may have been runtime suspended, thus i2c_dw_disable() hangs. Previously, I fixed this issue by separating ops for system pm and runtime pm, then in the system suspend/resume path, runtime pm apis are used to ensure the device is at correct state. But as Mika Westerberg pointed out: it sounds a bit silly to resume the device just because you want to call i2c_dw_disable() for it before suspending again. He then suggested an elegant solution which keeps the device runtime suspended during system suspend with the help of 'dev->power.direct_complete'. This patch adopted this solution, and in fact Mika provided the main code. Signed-off-by:
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Alexander Sverdlin authored
Use recovery framework and implement bus recovery using "Bus Monitor" register. Tests show that shortening SDA to GND results in "completion" timeout with "BUSY" bit still set, so initiate recovery in this case. Signed-off-by:
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Jarkko Nikula authored
sizeof(struct i2c_client) is 1088 bytes on a CONFIG_X86_64=y build and produces following warning when CONFIG_FRAME_WARN is set to 1024: drivers/i2c/i2c-core.c: In function ‘acpi_i2c_space_handler’: drivers/i2c/i2c-core.c:367:1: warning: the frame size of 1152 bytes is larger than 1024 bytes [-Wframe-larger-than=] This is not critical given that kernel stack is 16 kB on x86_64 but lets reduce the stack usage by allocating the struct i2c_client from the heap. Signed-off-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by:
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- 31 May, 2015 9 commits
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Shailendra Verma authored
Signed-off-by:
Shailendra Verma <shailendra.capricorn@gmail.com> Signed-off-by:
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Shailendra Verma authored
Signed-off-by:
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Shailendra Verma authored
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Eddie Huang authored
Add mediatek MT8173 I2C controller driver. Compare to I2C controller of earlier mediatek SoC, MT8173 fix write-then-read limitation, and also increase message size to 64kb. Signed-off-by:
Xudong Chen <xudong.chen@mediatek.com> Signed-off-by:
Liguo Zhang <liguo.zhang@mediatek.com> Signed-off-by:
Eddie Huang <eddie.huang@mediatek.com> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Xudong Chen authored
The mediatek SoCs have I2C controller that handle I2C transfer. This patch include common I2C bus driver. This driver is compatible with I2C controller on mt65xx/mt81xx. Signed-off-by:
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Wolfram Sang authored
int is vague, let's simply use the type of the variable in question. Signed-off-by:
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Wolfram Sang authored
Inform users what went wrong from the core, so drivers don't have to do it. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Wolfram Sang authored
There was some confusion what was needed to utilize the slave support, so let's be more precise about this. Add an introductory paragraph to the development section while we are here. Signed-off-by:
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Wolfram Sang authored
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