- 22 Jun, 2019 40 commits
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Charlene Liu authored
[Description] dcn2 use fixed clocks and not program DPP CLK or Disp_CLK. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Charlene Liu authored
for future use Signed-off-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by:
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Jun Lei authored
[why] value commited to by HW team is going to be higher than pre-silicon, and will cause underflow if driver not updated [how] update hardcoded value, update pstate switching logic to fix case where with long uclk time we won't allow switch even when we should Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] To prepare for the upcoming DRM plane color management properties we need to correct a lot of wrong behavior and assumptions made for CRTC color management. The documentation added by this commit in amdgpu_dm_color explains how the HW color pipeline works and its limitations with the DRM interface. The current implementation does the following wrong: - Implicit sRGB DGM when no CRTC DGM is set - Implicit sRGB RGM when no CRTC RGM is set - No way to specify a non-linear DGM matrix that produces correct output - No way to specify a correct RGM when a linear DGM is used We had workarounds for passing kms_color tests but not all of the behavior we had wrong was covered by these tests (especially when it comes to non-linear DGM). Testing both DGM and RGM at the same time isn't something kms_color tests well either. [How] The specifics for how color management works in AMDGPU and the new behavior can be found by reading the documentation added to amdgpu_dm_color.c from this patch. All of the incorrect cases from the old implementation have been addressed for the atomic interface, but there still a few TODOs for the legacy one. Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI. The result looks correct from visual inspection but the CRC no longer matches. For reference, the test was previously doing the following: linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ... Now the test is doing: linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ... Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Sun peng Li <Sunpeng.Li@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] This is meant to make it clearer that 0xf is not a valid OPP ID, and that code making use of OPP IDs should not accept this value. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by:
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Eric Bernstein authored
expose this function for future use Implementation of DCN3 DIO Link Encoder including dpcs register headers. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Charlene Liu authored
add dwb stereo caps and ver for future use Signed-off-by:
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Eric Bernstein authored
Add Alpha surface type for future use Signed-off-by:
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Jun Lei authored
[why] Existing behavior has overlapping ranges resulting in path dependent SMU selection [how] Make ranges non-overlapping, resulting in non-path dependent selection Signed-off-by:
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Wenjing Liu authored
[why] According to the latest specs, the max_target bpp sink can support is 16 bpp. [how] update dsc max_target_bpp to 16 Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Charlene Liu authored
required for new checks. Signed-off-by:
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Wenjing Liu authored
[why] Current policy assumes virtual DPCD peer device as an individual MST branch device with 1 input and 1 output. However this is only true for virtual DP-to-DP peer device. In general there are three types of virtual DP peer devices. 1. Sink peer device with virtual DPCD. 2. Virtual DP-to-DP Peer device with virtual DPCD. 3. Virtual DP-to-HDMI Protocol Converter Peer Device with Virtual DPCD. So we should break the assumption and handle all three types. [how] DP-to-DP peer device will have virtual DPCD cap upstream. Sink peer device will have virtual DPCD on the logical port. Dp to HDMI protocol converter peer device will have virtual DPCD on its converter port. For DSC capable Synaptics non VGA port we workaround by enumerating a virutal DPCD peer device on its upstream even if it doesn't have one. Signed-off-by:
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Jun Lei authored
[why] useful for debugging [how] plumb a debug option in dc Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Almost every function in DC that works with stream state expects that the current state on the stream is the one that it should be writing out. These functions are typically triggered by specifying a particular stream update - but the actual contents of the stream update itself are ignored, leaving it to the DM to actually update the stream state itself. The problem with doing this in DM is a matter of timing. On Linux most of this is incorrectly done in atomic check, when we actually want it to be done during atomic commit tail while access to DC is locked. To give an example, a commit requesting to modify color management state for DM could come in, be rejected, but still have modified the actual system state for the stream since it's shared memory. The next time color management gets programmed it'll use the rejected color management info - which might not even still be around if it's a custom transfer function. So a reasonable place to perform this is within DC itself and this is the model that's currently in use for surface updates. DC can even compare the current system state to the incoming surface update to determine update level, something that can't currnetly be done with the framework for stream updates. [How] Duplicate the framework used for surface updates for stream updates as well. Copy all the updates after checking the update type. Signed-off-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Ilya Bakoulin authored
SwathWidthCThisState is expected to be an unsigned int array. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Martin Leung authored
[why] when resetting pipes from 480p to dual-pipe 8k, modulo reg write for video optimized rate updated one pipe without changing the other, causing sync error [how] removed code from dcn2 Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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Ilya Bakoulin authored
[Why] The output_bpp pipe parameter was assigned an incorrect value (color depth enum), and subsequently used to overwrite the OutputBpp parameter calculated by DML. Seems like this had no effect except with DSC enabled, which would make DML produce bad outputs. [How] Removed assignment to OutputBpp, fixed output_bpp assignment, and properly set ForcedOutputLinkBPP instead of OutputBpp. Also removed condition in DML that prevented forcing of Output BPP with DSC enabled. Signed-off-by:
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Jun Lei authored
[why] VM implemenation is missing conversion from HW values in hubbub DM not passing actual PTB during flip [how] add proper HW conversion from logical values fix cases where we programmed VA even though we are in PA plumb in PTB from DM Signed-off-by:
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Ilya Bakoulin authored
Fixes for the following: - Incorrect pointer type (unsigned int instead of double) - Incorrect DSC number of slices setting Signed-off-by:
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Nikola Cornij authored
[why] Currently DSC power gating is disabled by default because the power transition doesn't happen, causing a crash on some systems [how] Fix the lack of power state transition and enable DSC power gating by default. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Charlene Liu authored
Should do full update when display writeback is updated. Signed-off-by:
Duke Du <Duke.Du@amd.com> Acked-by:
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Wenjing Liu authored
[why] dsc adjustment is allowed via stream update sequence. dsc enablement is only allowed via commit stream sequence. with the current unified dsc set function, it is hard to determine which sequence it is called by. The solution is to decouple dsc adjustment out of enablement sequence so we can handle them separately. [how] decouple dsc adjustment out of enablement. Signed-off-by:
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Jun Lei authored
[why] current DML logic uses currently trained setting for number of dp lanes in DML calculations. this is obviously flawed since just because 1 lane is in use doesn't mean only 1 lane can be used this causes mode validation to fail depending on current state, which is incorrect [how] DML should always assume 4 lanes are available. validation of bandwidth is not supposed to be handled by DML, since we do link validation without DML already also, DML is expecting there to be a copy of the max state, this state is removed when update_bounding_box is called to update actual SKU clocks. fix this as well by duping last state. Signed-off-by:
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Wesley Chalmers authored
[WHY] DCN code should make as few references to DCE as possible [HOW] Copy DCE110 implementation of find_first_free_match_stream_enc_for_link into DCN10 Signed-off-by:
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Wesley Chalmers authored
[WHY] From DCE110 onward, we have the ability to assign DIG BE and FE separately for any display connector type; before, we could only do this for DP. Signed-off-by:
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Nikola Cornij authored
[why] With DSC power gating enabled, one of the register reads times out occasionally, causing a DSC test to fail. [how] Disable DSC power gating in Diags. NOTE: This has to be reverted once the problems with DSC power gating are resolved. Signed-off-by:
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Joshua Aberback authored
[Why] We want a test pattern to show up on screen when we're blanked and have visual confirm enabled, for debugging. Raven does this, it's a mistake that Navi does not. [How] - in "blank_pixel_data", set appropriate DPG pattern for visual confirm - refactor DPG calls out of "enable_stream_timing" Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
* add plane state null checks * add and set update surface flags Signed-off-by:
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Tyler DiBattista authored
[Why] these enums/structs will be used more generically in the future so moving it to dc_hw_types and dc_types Signed-off-by:
Tyler DiBattista <tyler.dibattista@amd.com> Reviewed-by:
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Vitaly Prosyak authored
[Why & How] Reuse existent code path (dcn1+) and in order to do that apply de gamma in 1D blender LUT and re use MPC OGAM. Follow up is required. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Charlene Liu authored
[Description] Features that are desirable for minimizing the Global Sync Period: DRR and lateflip Signed-off-by:
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Wenjing Liu authored
Signed-off-by:
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Wenjing Liu authored
[why] In compute dsc bandwidth range there is an uninitialized variable [how] Initialize the variable to the correct value. Signed-off-by:
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Leo (Hanghong) Ma authored
[Why] To send sdp message immediately from a single slot. [How] Modify the generic SDP message interface, and use GSP4 to send immediate sdp message. Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
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Ilya Bakoulin authored
DCN2.0 LB BPP should be 48 or 16BPC and max cursor width should be 256. Also use populate_dml_pipes as functions pointer instead of using it directly Signed-off-by:
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Dmytro Laktyushkin authored
A regression was introduced when we set correct tile size for the gfx9 swizzle mode. This resulted in incorrect macro tile size. Signed-off-by:
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Joshua Aberback authored
[Why] Plane disable gets calls when we enable blank. On DCN2, we blank by using DPG to display a black colour instead of using OTG blank. DPG runs off the OPP clock, therefore we shouldn't disable the OPP clock when disabling the plane. We do need to disable the OPP clock when disabling the entire pipe, that will be addressed in a separate commit. Signed-off-by:
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Dmytro Laktyushkin authored
It looks like mpo isn't properly disabled during odm, this change is meant to fix that. Signed-off-by:
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Charlene Liu authored
dwb fixes. Signed-off-by:
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Charlene Liu authored
[Description] dcn20 has num_dwb =1 in the res cap, but not created. Signed-off-by:
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