- 04 Jun, 2018 11 commits
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Stephen Boyd authored
* clk-qcom-8996-halt: clk: qcom: gcc-msm8996: Disable halt check on UFS clocks clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk
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Stephen Boyd authored
* clk-qcom-sdm845: clk: qcom: Export clk_fabia_pll_configure() clk: qcom: Add video clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Video clock bindings clk: qcom: Add Global Clock controller (GCC) driver for SDM845 clk: qcom: Add DT bindings for SDM845 gcc clock controller clk: qcom: Configure the RCGs to a safe source as needed clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks clk: qcom: Simplify gdsc status checking logic clk: qcom: gdsc: Add support to poll CFG register to check GDSC state clk: qcom: gdsc: Add support to poll for higher timeout value clk: qcom: gdsc: Add support to reset AON and block reset logic clk: qcom: Add support for controlling Fabia PLL clk: qcom: Clear hardware clock control bit of RCG Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the description and also the video Kconfig says things slightly differently from the GCC one so just make it the same.
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Stephen Boyd authored
Merge branches 'clk-match-string', 'clk-ingenic', 'clk-si544-round-fix' and 'clk-bcm-stingray' into clk-next * clk-match-string: clk: use match_string() helper clk: bcm2835: use match_string() helper * clk-ingenic: clk: ingenic: jz4770: Add 150us delay after enabling VPU clock clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle clk: ingenic: jz4770: Change OTG from custom to standard gated clock clk: ingenic: Support specifying "wait for clock stable" delay clk: ingenic: Add support for clocks whose gate bit is inverted * clk-si544-round-fix: clk-si544: Properly round requested frequency to nearest match * clk-bcm-stingray: clk: bcm: Update and add Stingray clock entries dt-bindings: clk: Update Stingray binding doc
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Stephen Boyd authored
Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and 'clk-debugfs-simple' into clk-next * clk-imx7d: clk: imx7d: reset parent for mipi csi root clk: imx7d: fix mipi dphy div parent * clk-hisi-stub: clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB * clk-mvebu: clk: mvebu: use correct bit for 98DX3236 NAND * clk-imx6-epit: clk: imx6: add EPIT clock support * clk-debugfs-simple: clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions
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Stephen Boyd authored
* clk-imx6sx: clk: imx6sl: correct ocram_podf clock type clk: imx6sx: disable unnecessary clocks during clock initialization clk: imx6sx: add missing lvds2 clock to the clock tree * clk-imx7d-enet: ARM: dts: imx7: correct enet ipg clock clk: imx7d: correct enet clock CCGR registers clk: imx7d: correct enet phy ref clock gates * clk-aspeed-24: clk: aspeed: Add 24MHz fixed clock
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Stephen Boyd authored
Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' and 'clk-qcom-mmagic' into clk-next * clk-allwinner: clk: sunxi-ng: r40: export a regmap to access the GMAC register clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: add support for H6 PRCM CCU * clk-rockchip: clk: rockchip: remove deprecated gate-clk code and dt-binding clk: rockchip: use match_string() helper * clk-tegra: clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 clk: tegra20: Correct parents of CDEV1/2 clocks clk: tegra20: Add DEV1/DEV2 OSC dividers * clk-berlin: clk: berlin: switch to SPDX license identifier * clk-qcom-mmagic: clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled clk: qcom: Register the gdscs before the clocks clk: qcom: gdsc: Add support for ALWAYS_ON gdscs
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Stephen Boyd authored
Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next * clk-hisi-usb: clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC * clk-silent-bulk: clk: bulk: silently error out on EPROBE_DEFER * clk-mtk-hdmi: clk: mediatek: correct the clocks for MT2701 HDMI PHY module * clk-mtk-mali: clk: mediatek: add g3dsys support for MT2701 and MT7623 dt-bindings: reset: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add g3dsys bindings * clk-imx6ul-ccosr: clk: imx: Add new clo01 and clo2 controlled by CCOSR
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Stephen Boyd authored
Merge branches 'clk-stm32mp1', 'clk-samsung', 'clk-uniphier-mpeg', 'clk-stratix10' and 'clk-aspeed' into clk-next * clk-stm32mp1: clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()' clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock clk: stm32mp1: remove ck_apb_dbg clock clk: stm32mp1: set stgen_k clock as critical clk: stm32mp1: add missing tzc2 clock clk: stm32mp1: fix SAI3 & SAI4 clocks clk: stm32mp1: remove unused dfsdm_src[] const clk: stm32mp1: add missing static * clk-samsung: clk: samsung: simplify getting .drvdata * clk-uniphier-mpeg: clk: uniphier: add LD11/LD20 stream demux system clock * clk-stratix10: clk: socfpga: stratix10: suppress unbinding platform's clock driver clk: socfpga: stratix10: use platform driver APIs * clk-aspeed: clk:aspeed: Fix reset bits for PCI/VGA and PECI clk: aspeed: Support second reset register
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Stephen Boyd authored
Merge branches 'clk-qcom-rpmh', 'clk-npcm7xx', 'clk-of-parent-count' and 'clk-qcom-rcg-fix' into clk-next * clk-qcom-rpmh: dt-bindings: clock: Introduce QCOM RPMh clock bindings * clk-npcm7xx: clk: npcm7xx: fix return value check in npcm7xx_clk_init() clk: npcm7xx: add clock controller dt-binding: clk: npcm750: Add binding for Nuvoton NPCM7XX Clock * clk-of-parent-count: pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding soc/tegra: pmc: Use of_clk_get_parent_count() instead of open coding soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding ARM: timer-sp: Use of_clk_get_parent_count() instead of open coding clk: Extract OF clock helpers in <linux/of_clk.h> * clk-qcom-rcg-fix: clk: qcom: Base rcg parent rate off plan frequency
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Stephen Boyd authored
* clk-actions: clk: actions: Add S900 SoC clock support clk: actions: Add pll clock support clk: actions: Add composite clock support clk: actions: Add fixed factor clock support clk: actions: Add factor clock support clk: actions: Add divider clock support clk: actions: Add mux clock support clk: actions: Add gate clock support clk: actions: Add common clock driver support dt-bindings: clock: Add Actions S900 clock bindings
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Stephen Boyd authored
* clk-warn: clk: Print the clock name and warning cause * clk-core: clk: Remove clk_init_cb typedef * clk-spear: clk: spear: fix WDT clock definition on SPEAr600 * clk-qcom-msm8998: clk: qcom: Add MSM8998 Global Clock Control (GCC) driver
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- 02 Jun, 2018 19 commits
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Stephen Boyd authored
This is used by the video clk driver on sdm845 and that's a module. Export it to prevent module build failures. Signed-off-by:Stephen Boyd <sboyd@kernel.org>
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Pramod Kumar authored
Update and add Stingray clock definitions and tables so they match the binding document and the latest ASIC datasheet Signed-off-by:
Pramod Kumar <pramod.kumar@broadcom.com> Signed-off-by:
Ray Jui <ray.jui@broadcom.com> Signed-off-by:
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Pramod Kumar authored
Update Stingray clock binding document to add additional clock entries with names matching the latest ASIC datasheet. Also modify a few existing entries to make their naming more consistent with the rest of the entries Signed-off-by:
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Mike Looijmans authored
The si544 driver had a rounding problem that using the result of clk_round_rate may set the clock to yet another rate, for example: clk_round_rate(195000000) = 194999999 clk_round_rate(194999999) = 194999998 Clients would expect that after clk_set_rate(clk, freq2=clk_round_rate(clk, freq)) the chip will be running at exactly freq2. The problem was in the calculation of the feedback divider, it was always rounded down instead of to the nearest possible VCO value. After this change, the following holds true for any supported frequency: actual_freq = clk_round_rate(clk, freq); clk_set_rate(clk, actual_freq); clk_round_rate(clk, actual_freq) == actual_freq && clk_get_rate(clk) == actual_freq Signed-off-by:
Mike Looijmans <mike.looijmans@topic.nl> Fixes: 953cc3e8 ("clk: Add driver for the si544 clock generator chip") Signed-off-by:
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Paul Cercueil authored
This is required, as we must not use the AHB1 bus before it is stable. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
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Paul Cercueil authored
This was broken before, because the AHB1 bus was enabled before the VPU clock was ungated, while it must be done afterwards. Signed-off-by:
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Paul Cercueil authored
When the main processor goes idle, by default its clock is stopped. However, this also stops the clock of the co-processor. Here, if the C1CLK clock is enabled, we disable this functionality. Signed-off-by:
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Paul Cercueil authored
We now have the means to express the specificities of the OTG clock with the common CGU code. Signed-off-by:
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Paul Cercueil authored
Some clocks need a small delay after being ungated to run stable, as using them too soon might result in hardware lockups. Signed-off-by:
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Paul Cercueil authored
Support the clocks which are gated when their gate bit is cleared instead of set. Signed-off-by:
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Yisheng Xie authored
match_string() returns the index of an array for a matching string, which can be used instead of open coded variant. Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Signed-off-by:
Yisheng Xie <xieyisheng1@huawei.com> Signed-off-by:
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Yisheng Xie authored
match_string() returns the index of an array for a matching string, which can be used instead of open coded variant. Reviewed-by:
Eric Anholt <eric@anholt.net> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Eric Anholt <eric@anholt.net> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: linux-clk@vger.kernel.org Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by:
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Stephen Boyd authored
We only have two users of the debug_init hook, and we recently stopped caring about the return value from that op. Finish that off by changing the clk_op to return void instead of int because it doesn't matter if debugfs fails or not. Cc: Eric Anholt <eric@anholt.net> Cc: David Lechner <david@lechnology.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: -
Greg Kroah-Hartman authored
No one was using this api call, so remove it. If it is ever needed in the future, a "raw" debugfs call can be used. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
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Greg Kroah-Hartman authored
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. The return value of these functions were never checked in the end anyway, so it is obvious this does not change any functionality :) Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by:
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Greg Kroah-Hartman authored
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Acked-by:
David Lechner <david@lechnology.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by:
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Greg Kroah-Hartman authored
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by:
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Greg Kroah-Hartman authored
When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. This cleans up the init code a lot, and there's no need to return an error value based on the debugfs calls, especially as it turns out no one was even looking at that return value. So it obviously wasn't that important :) Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by:
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Colin Didier authored
Add EPIT clock support to the i.MX6Q clocking infrastructure. Signed-off-by:
Colin Didier <colin.didier@devialet.com> Signed-off-by:
Clément Peron <clement.peron@devialet.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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- 01 Jun, 2018 10 commits
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Chris Packham authored
The correct fieldbit value for the NAND PLL reload trigger is 27. Fixes: commit e120c17a ("clk: mvebu: support for 98DX3236 SoC") Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by:
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Daniel Lezcano authored
The current defconfig is inconsistent as it selects the mailbox and the clock for the hi6220 and the hi3660 without having their Kconfigs making sure the dependencies are correct. It ends up when selecting different versions for the kernel (for example when git bisecting) those options disappear and they don't get back, leading to unexpected behaviors. In our case, the cpufreq driver does no longer work because the clock fails to initialize due to the clock stub and the mailbox missing. In order to have the dependencies correctly set when defaulting, let's do the same as commit 3a49afb8 ("clk: enable hi655x common clk automatically") where we select automatically the driver when the parent driver is selected. With sensible defaults in place, we can leave other choices for EXPERT. Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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Rui Miguel Silva authored
To guarantee that we do not get Overflow in image FIFO the outer bandwidth has to be faster than inputer bandwidth. For that it must be possible to set a faster frequency clock. So set new parent to sys_pfd3 clock for the mipi csi block. Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by:
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Rui Miguel Silva authored
Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan clock and set the correct parent. before: cat clk_orphan_summary enable prepare protect clock count count count rate accuracy phase ---------------------------------------------------------------------------------------- mipi_dphy_post_div 1 1 0 0 0 0 mipi_dphy_root_clk 1 1 0 0 0 0 cat clk_dump | grep mipi_dphy mipi_dphy_post_div 1 1 0 0 0 0 mipi_dphy_root_clk 1 1 0 0 0 0 after: cat clk_dump | grep mipi_dphy mipi_dphy_src 1 1 0 24000000 0 0 mipi_dphy_cg 1 1 0 24000000 0 0 mipi_dphy_pre_div 1 1 0 24000000 0 0 mipi_dphy_post_div 1 1 0 24000000 0 0 mipi_dphy_root_clk 1 1 0 24000000 0 0 Fixes: 8f6d8094 ("ARM: imx: add imx7d clk tree support") Acked-by:Dong Aisheng <Aisheng.dong@nxp.com> Signed-off-by:
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Bjorn Andersson authored
The halt check of the UFS symbol clocks always fails, as such probing UFS after clk_disable_unused always fails. This makes it impossible to boot a system with the UFS phy or UFS HCD drivers compiled as modules. Follow SDM845 and disable the halt check on these clocks. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
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Lei YU authored
Add a 24MHz fixed clock. This clock will be used for certain devices, e.g. pwm. Signed-off-by:
Lei YU <mine260309@gmail.com> Reviewed-by:
Joel Stanley <joel@jms.id.au> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Anson Huang authored
ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus clock. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Anson Huang authored
Correct enet clock gates as below: CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK Just rename unused IMX7D_ENETx_REF_ROOT_CLK for IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by:
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Anson Huang authored
IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly, there is no clock gate after it, rename it to IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change. Signed-off-by:
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Anson Huang authored
IMX6SL_CLK_OCRAM_PODF is a busy divider, its name in CCM_CDHIPR register of Reference Manual CCM chapter is axi_podf_busy, correct its clock type. Signed-off-by:
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