- 02 May, 2016 32 commits
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Nicolai Stange authored
The values of all but the RADEON_HPD_NONE members of the radeon_hpd_id enum transform 1:1 into bit positions within the 'enabled' bitset as assembled by evergreen_hpd_init(): enabled |= 1 << radeon_connector->hpd.hpd; However, if ->hpd.hpd happens to equal RADEON_HPD_NONE == 0xff, UBSAN reports UBSAN: Undefined behaviour in drivers/gpu/drm/radeon/evergreen.c:1867:16 shift exponent 255 is too large for 32-bit type 'int' [...] Call Trace: [<ffffffff818c4d35>] dump_stack+0xbc/0x117 [<ffffffff818c4c79>] ? _atomic_dec_and_lock+0x169/0x169 [<ffffffff819411bb>] ubsan_epilogue+0xd/0x4e [<ffffffff81941cbc>] __ubsan_handle_shift_out_of_bounds+0x1fb/0x254 [<ffffffffa0ba7f2e>] ? atom_execute_table+0x3e/0x50 [radeon] [<ffffffff81941ac1>] ? __ubsan_handle_load_invalid_value+0x158/0x158 [<ffffffffa0b87700>] ? radeon_get_pll_use_mask+0x130/0x130 [radeon] [<ffffffff81219930>] ? wake_up_klogd_work_func+0x60/0x60 [<ffffffff8121a35e>] ? vprintk_default+0x3e/0x60 [<ffffffffa0c603c4>] evergreen_hpd_init+0x274/0x2d0 [radeon] [<ffffffffa0c603c4>] ? evergreen_hpd_init+0x274/0x2d0 [radeon] [<ffffffffa0bd196e>] radeon_modeset_init+0x8ce/0x18d0 [radeon] [<ffffffffa0b71d86>] radeon_driver_load_kms+0x186/0x350 [radeon] [<ffffffffa03b6b16>] drm_dev_register+0xc6/0x100 [drm] [<ffffffffa03bc8c4>] drm_get_pci_dev+0xe4/0x490 [drm] [<ffffffff814b83f0>] ? kfree+0x220/0x370 [<ffffffffa0b687c2>] radeon_pci_probe+0x112/0x140 [radeon] [...] ===================================================================== radeon 0000:01:00.0: No connectors reported connected with modes At least on x86, there should be no user-visible impact as there 1 << 0xff == 1 << (0xff & 31) == 1 << 31 holds and 31 > RADEON_MAX_HPD_PINS. Thus, this patch is a cosmetic one. All of the above applies analogously to evergreen_hpd_fini(), r100_hpd_init(), r100_hpd_fini(), r600_hpd_init(), r600_hpd_fini(), rs600_hpd_init() and rs600_hpd_fini() Silence UBSAN by checking ->hpd.hpd for RADEON_HPD_NONE before oring it into the 'enabled' bitset in the *_init()- or the 'disabled' bitset in the *_fini()-functions respectively. Signed-off-by:
Nicolai Stange <nicstange@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rex Zhu authored
White space fix. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Rex Zhu authored
This is not a fatal error. v2: add comment why ignore the error here. Signed-off-by:
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Rex Zhu authored
Need to soft reset VCE as part of the clockgating sequence. Signed-off-by:
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Monk Liu authored
this is to fix fatal page fault error that occured if: job is signaled/released after its timeout work is already put to the global queue (in this case the cancel_delayed_work will return false), which will lead to NX-protection error page fault during job_timeout_func. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Monk Liu authored
Add two callbacks to scheduler to maintain jobs, and invoked for job timeout calculations. Now TDR measures time gap from job is processed by hw. v2: fix typo Signed-off-by:
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Monk Liu authored
original time out detect routine is incorrect, cuz it measures the gap from job scheduled, but we should only measure the gap from processed by hw. Signed-off-by:
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Monk Liu authored
the mirror_list will be used for later time out detect feature. This is needed to properly detect a GPU timeout with the scheduler. Signed-off-by:
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Monk Liu authored
for those jobs submitted through scheduler, do not free it immediately after scheduled, instead free it in global workqueue by its sched fence signaling callback function. v2: call uf's bo_undef after job_run() call job's sync free after job_run() no static inline __amdgpu_job_free() anymore, just use kfree(job) to replace it. Signed-off-by:
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Vitaly Prosyak authored
Fixed mc stop and resume hardware programming sequence. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
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Monk Liu authored
Consolidate job initialization in one place rather than duplicating it in multiple places. Signed-off-by:
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Monk Liu authored
More ground work for conditional execution on SDMA necessary for preemption. Signed-off-by:
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Monk Liu authored
This adds the groundwork for conditional execution on SDMA which is necessary for preemption. Signed-off-by:
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Chunming Zhou authored
V2: the signaled items on the LRU maintain their order Signed-off-by:
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Nils Wallménius authored
Signed-off-by:
Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by:
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Nils Wallménius authored
It is only used locally in amdgpu_get_bios Signed-off-by:
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Nils Wallménius authored
Signed-off-by:
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Nils Wallménius authored
Signed-off-by:
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Jérome Glisse authored
Some GPU block like UVD and VCE require hard reset to be properly resume if there is no real powerdown of the asic like during various hibernation step. This patch perform such hard reset. Reviewed-by:
Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by:
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Jérome Glisse authored
In some cases, like when freezing for hibernation, we need to be able to force hard reset even if no engine are stuck. This patch add a bool option to current asic reset callback to allow to force hard reset on asic that supports it. Reviewed-by:
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Jérome Glisse authored
Quite few suspend/hibernation bugs are related to this block. Add an option to disable those as a work around. Reviewed-by:
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Jérome Glisse authored
Quite few suspend/hibernation bugs are related to this block. Add an option to disable those as a work around. Reviewed-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_vce doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_vce doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_vce doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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Jérome Glisse authored
This will later on serve for module option to disable vce. Reviewed-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_uvd doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_uvd doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_uvd doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_uvd doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_uvd doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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Jérome Glisse authored
This match the exact same control flow as existing code. It just use goto instead of multiple levels of if/else. It also clarify early initialization failures by clearing rdev->has_uvd doing so does not change end result from hardware point of view, it only avoids printing more error messages down the line and thus only the original error is reported. Acked-by:
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- 29 Apr, 2016 2 commits
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http://git.agner.ch/git/linux-drm-fsl-dcuDave Airlie authored
This adds very rudimentary TCON (timing controller for raw LCD displays) support to enable the bypass mode in order to use the DCU controller on Freescale/NXP Vybrid SoC's. Additionally the register clock and pixel clock has been separated, but are currently still enabled and disabled pairwise. Other than that, fixes and cleanups accross the driver. * 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu: drm/fsl-dcu: increment version and date drm/fsl-dcu: implement lastclose callback drm/fsl-dcu: disable output polling on driver unload drm/fsl-dcu: deallocate fbdev CMA on unload drm/fsl-dcu: use variable name dev for struct drm_device drm/fsl-dcu: handle missing panel gracefully drm/fsl-dcu: detach panel on destroy drm/layerscape: reduce excessive stack usage drm/fsl-dcu: add TCON driver drm/fsl-dcu: use common clock framework for pixel clock divider drm/fsl-dcu: add extra clock for pixel clock drm/fsl-dcu: disable clock on initialization failure and remove
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Dave Airlie authored
Merge tag 'sun4i-drm-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into drm-next Allwinner DRM driver for 4.7 This pull request introduces the sun4i driver, meant to be used on the older Allwinner SoCs (A10, A13, A20, A23, A31 and A33). It currently supports only the A13, which has one of the simplest video pipeline. Support for other video components and SoCs will be added eventually. It supports only a RGB or composite output. It doesn't do HDMI, VGA, LVDS or power management yet, but that will come in time as well. * tag 'sun4i-drm-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: MAINTAINERS: Add a maintainer for the Allwinner DRM driver drm: sun4i: tv: Add NTSC output standard drm: sun4i: tv: Add PAL output standard drm: sun4i: Add composite output drm: sun4i: Add RGB output drm: Add Allwinner A10 Display Engine support drm: sun4i: Add DT bindings documentation drm: fb: Add seq_file definition
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- 28 Apr, 2016 6 commits
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Maxime Ripard authored
Add myself as the maintainer of the new Allwinner DRM driver. Signed-off-by:Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Add the settings to support the NTSC standard. Reviewed-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
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Maxime Ripard authored
Now that we have support for the composite output, we can start adding new supported standards. Start with PAL, and we will add other eventually. Reviewed-by:
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Maxime Ripard authored
Some Allwinner SoCs have an IP called the TV encoder that is used to output composite and VGA signals. In such a case, we need to use the second TCON channel. Add support for that TV encoder. Reviewed-by:
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Maxime Ripard authored
One of the A10 display pipeline possible output is an RGB interface to drive LCD panels directly. This is done through the first channel of the TCON that will output our video signals directly. Reviewed-by:
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Maxime Ripard authored
The Allwinner A10 and subsequent SoCs share the same display pipeline, with variations in the number of controllers (1 or 2), or the presence or not of some output (HDMI, TV, VGA) or not. Add a driver with a limited set of features for now, and we will hopefully support all of them eventually Reviewed-by:
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