- 16 Apr, 2010 40 commits
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by:
John W. Linville <linville@tuxdriver.com>
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Vasanthakumar Thiagarajan authored
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Felix Fietkau <nbd@openwrt.org> Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
Store appropriate desc length which will be used by the ath9k module while duplicating tx desc. Signed-off-by:
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Luis R. Rodriguez authored
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Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by:
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Felix Fietkau authored
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
The AR9003 hardware family now initializes hardware by block components and into stages: pre, core and init. Signed-off-by:
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Luis R. Rodriguez authored
The initvals.h file is over 7000 lines now, so instead of adding AR9003 initvals to it instead lets split the current initvals.h by hardware family: AR5008, AR9001, AR9002 The AR9003 family will have its own initval file later. Signed-off-by:
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Felix Fietkau authored
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Felix Fietkau authored
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Felix Fietkau authored
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Luis R. Rodriguez authored
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Felix Fietkau authored
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Senthil Balasubramanian authored
Also, no need for the udelay(2) on AR9003 hardware. Signed-off-by:
Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by:
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Senthil Balasubramanian authored
The AR9003 family requires a change on the loop and can also skip testing the PHY timing registers. This chip test can now be used by all Atheros hardware families, including legacy. We can eventually move this out to the generic ath module. Signed-off-by:
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Vasanthakumar Thiagarajan authored
* Set rx buf size in register 0x60 * Set rxdp on the respective hw rx queue (HP and LP queues) * Process rx descriptor Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
HP & LP queue depth and rx status length. Signed-off-by:
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Vasanthakumar Thiagarajan authored
AR9003 supports extended DMA (EDMA), this comes with some bells and whistles on top of the legacy DMA that we are used to. Mark AR9003 and later chips EDMA capable. Signed-off-by:
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
ANI is still being debugged on AR9003 by our systems team so it should not yet be enabled yet. When ANI will be enabled all ANI functionality is expected to be enabled so fill the ANI functionality to all for AR9003 for now as well. Cc: Enis Akay <Enis.Akay@atheros.com> Signed-off-by:
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
This allows us to add SREV checks on these helpers. Signed-off-by:
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Luis R. Rodriguez authored
This add stubs for PHY support for the AR9003 hardware family. Signed-off-by:
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Senthil Balasubramanian authored
Also, clean up and reorganize the AR9287 macro to have better ordering. We won't add the PCI ID to the supported device list until we have some functional code for it. Signed-off-by:
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Luis R. Rodriguez authored
The PLL control computation used to program the AR_RTC_PLL_CONTROL register varies between our harware so just add a private callback for it. AR9003 will use its own callback. Signed-off-by:
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
This is not required for the AR9003 family. Signed-off-by:
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Luis R. Rodriguez authored
The PHY split is easier done in a few steps. First move the RF ops to the private ops and rename them accordingly. We split PHY stuff up first for the AR5008 and AR9002 families. There are some callbacks that AR9002 share with the AR5008 familiy so we set those first, if AR9002 has some different callbacks it will override them upon hardware init. Signed-off-by:
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Luis R. Rodriguez authored
This is used only once by ath9k_hw_process_ini() to write an array of phy registers through REG_WRITE_ARRAY(), but we already call REG_WRITE_ARRAY() multiple times on the same caller so just remove this pointless wrapper. We'll eventually just move the ath9k_hw_process_ini() caller as an callback to abstract away between different hardware families. Although this change is subtle I should note that this does change the delay pattern on writing the next series of registers. REG_WRITE_ARRAY() uses a counter for each register write and does a udelay(1) every 64 writes. By removing this call it means that the counter is processed for all the iniBB_RfGain registers and is incremented on ath9k_hw_process_ini(), before this the after the call ath9k_hw_write_regs() was made the register counter was kept at the same index number prior to the call. Signed-off-by:
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Luis R. Rodriguez authored
AR9003 does not have a reset control for AHB. Signed-off-by:
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Felix Fietkau authored
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Felix Fietkau authored
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Felix Fietkau authored
This is not a stable code fix as this register is not used anywhere. Signed-off-by:
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Felix Fietkau authored
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