- 24 Apr, 2018 31 commits
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Daniel Vetter authored
There's nothing tinydrm specific to this, and there's a few more copies of the same in various other drivers. Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Cc: Gustavo Padovan <gustavo@padovan.org> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: David Airlie <airlied@linux.ie> Cc: David Lechner <david@lechnology.com> Cc: "Noralf Trønnes" <noralf@tronnes.org> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Daniel Stone <daniels@collabora.com> Cc: Haneen Mohammed <hamohammed.sa@gmail.com> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com> Reviewed-by:
Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Acked-by:
David Lechner <david@lechnology.com> Reviewed-by:
Noralf Trønnes <noralf@tronnes.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180405154449.23038-3-daniel.vetter@ffwll.ch
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Daniel Vetter authored
Less hits to go through when I git grep over all drivers. These callbacks are optional. Signed-off-by:
Thomas Hellstrom <thellstrom@vmware.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180405154449.23038-2-daniel.vetter@ffwll.ch
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Hans de Goede authored
The Lenovo Ideapad Mixx 320 laptop uses a portrait LCD panel, add a quirk for this. While at it instead of duplicating the same drm_dmi_panel_orientation_data for 3 laptops add a generic lcd800x1280_rightside_up orientation_data and use that for all 3 (including the new Mixx 320 entry). Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180418123642.11088-2-hdegoede@redhat.com
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Hans de Goede authored
Some production batches of the Lenovo Ideapad Mixx 310 laptop use a portrait LCD panel, add a quirk for this. Reviewed-by:
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Tomasz Figa authored
It is not used anymore after last changes and it was not even correct to begin with as it assumed a 1:1 relation between a CRTC and encoder, while in fact a CRTC can be attached to multiple encoders. Signed-off-by:
Tomasz Figa <tfiga@chromium.org> Signed-off-by:
Thierry Escande <thierry.escande@collabora.com> Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
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Tomasz Figa authored
Currently PSR flush is triggered from CRTC's .atomic_begin() callback, which is executed after modeset disables and enables and before plane updates are committed. Since PSR flush and re-enable can be triggered asynchronously by external sources (input event, delayed work), it can race with hardware programming done in the aforementioned stages. This patch blocks the PSR completely before hardware programming part begins and unblock after it ends. This relies on reference counted PSR disable introduced with previous patch. Cc: Kristian H. Kristensen <hoegsberg@chromium.org> Signed-off-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
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Tomasz Figa authored
Currently both rockchip_drm_psr_activate() and _deactivate() only set the boolean "active" flag without actually making sure that hardware state complies with it. Since we are going to extend the usage of this API to properly lock PSR for the duration of atomic commits, we change the semantics in following way: - a counter is used to track the number of inhibit requests, - PSR is actually disabled in hardware on first inhibit request, - PSR enable work is scheduled on last allow request. The above allows using the API as a way to deterministically synchronize PSR state changes with other DRM events, i.e. atomic commits and cursor updates. As a nice side effect, the naming is sorted out and we have "inhibit" for stopping the software logic and "enable" for hardware state. Signed-off-by:
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Tomasz Figa authored
The first time after we call rockchip_drm_do_flush() after rockchip_drm_psr_register(), we go from PSR_DISABLE to PSR_FLUSH. The difference between PSR_DISABLE and PSR_FLUSH is whether or not we have a delayed work pending - PSR is off in either state. However psr_set_state() only catches the transition from PSR_FLUSH to PSR_DISABLE (which never happens), while going from PSR_DISABLE to PSR_FLUSH triggers a call to psr->set() to disable PSR while it's already disabled. This triggers the eDP PHY power-on sequence without being shut down first and this seems to occasionally leave the encoder unable to later enable PSR. Let's just simplify the state machine and simply consider PSR_DISABLE and PSR_FLUSH the same state. Signed-off-by:
Kristian H. Kristensen <hoegsberg@chromium.org> Signed-off-by:
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Tomasz Figa authored
Driver callbacks, such as system suspend or resume can be called any time, specifically they can be called before the component bind callback. Let's use dp->adp pointer as a safeguard and skip calling Analogix entry points if it is an ERR_PTR(). Signed-off-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
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Douglas Anderson authored
Some of the platform-specific stuff in rockchip_dp_poweron() needs to happen before the generic code. Some needs to happen after. Let's split the callback in two. Specifically we can't start doing PSR work until _after_ the whole controller is up, so don't set the enable until the end. Cc: Kristian H. Kristensen <hoegsberg@chromium.org> Signed-off-by:
Douglas Anderson <dianders@chromium.org> [seanpaul added exynos change] Signed-off-by:
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Mark Yao authored
Some encoder have a crc verification check, crc check fail if input and output data is not equal. That means encoder input and output need use same color depth, vop can output 10bit data to encoder, but some panel only support 8bit depth, that would make crc check die. So pre dither down vop data to 8bit if panel's bpc is 8. Signed-off-by:
Mark Yao <mark.yao@rock-chips.com> [seanpaul resolved conflict in rockchip_drm_vop.c] Signed-off-by:
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Douglas Anderson authored
The comments in analogix_dp_init_aux() claim that we're disabling aux channel retries, but then right below it for Rockchip it sets them to 3. If we actually need 3 retries for Rockchip then we could adjust the comment, but it seems more likely that we want the same retry behavior across all platforms. Cc: Stéphane Marchesin <marcheu@chromium.org> Cc: 征增 王 <wzz@rock-chips.com> Signed-off-by:
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Douglas Anderson authored
The code in analogix_dp_transfer() that was supposed to print out: AUX CH error happened Was actually dead code. That's because the previous check (whether the interrupt status indicated any errors) would have hit for all errors anyway. Let's combine the two error checks so we can actually see AUX CH errors. We'll also downgrade the message to a warning since some of these types of errors might be expected for some displays. If this gets too noisy we can downgrade again to debug. Cc: 征增 王 <wzz@rock-chips.com> Signed-off-by:
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Douglas Anderson authored
The current user of the analogix power_off is "analogix_dp-rockchip". That driver does this: - deactivate PSR - turn off a clock Both of these things (especially deactive PSR) should be done before we turn the PHY power off and turn off analog power. Let's move the callback up. Note that without this patch (and with https://patchwork.kernel.org/patch/9553349/ [seanpaul: this patch was not applied, but it seems like the race can still occur]), I experienced an error in reboot testing where one thread was at: rockchip_drm_psr_deactivate rockchip_dp_powerdown analogix_dp_bridge_disable drm_bridge_disable ...and the other thread was at: analogix_dp_send_psr_spd analogix_dp_enable_psr analogix_dp_psr_set psr_flush_handler The flush handler thread was finding AUX channel errors and eventually reported "Failed to apply PSR", where I had a kgdb breakpoint. Presumably the device would have eventually given up and shut down anyway, but it seems better to fix the order to be more correct. Cc: Kristian H. Kristensen <hoegsberg@chromium.org> Signed-off-by:
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zain wang authored
It's too early to detect fast link training, if other step after it failed, we will set fast_link flag to 1, and retry set_bridge again. In this case we will power down and power up panel power supply, and we will do fast link training since we have set fast_link flag to 1. In fact, we should do full link training now, not the fast link training. So we should move the fast link detection at the end of set_bridge. Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by:
zain wang <wzz@rock-chips.com> Signed-off-by:
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zain wang authored
Register ANALOGIX_DP_FUNC_EN_1(offset 0x18), Rockchip is different to Exynos: on Exynos edp phy, BIT 7 MASTER_VID_FUNC_EN_N BIT 6 reserved BIT 5 SLAVE_VID_FUNC_EN_N on Rockchip edp phy, BIT 7 reserved BIT 6 RK_VID_CAP_FUNC_EN_N BIT 5 RK_VID_FIFO_FUNC_EN_N So, we should do some private operations to Rockchip. Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by:
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zain wang authored
The STRM_VALID bit in register ANALOGIX_DP_SYS_CTL_3 may be unstable, so we may hit the error log "Timeout of video streamclk ok" since checked this unstable bit. In fact, we can go continue and the streamclk is ok if we wait enough time, it does no effect on display. Let's change this error to warn. Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
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zain wang authored
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power instead of ANALOGIX_DP_PLL_CTL. Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
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zain wang authored
If we failed disable psr, it would hang the display until next psr cycle coming. So we should restore psr->state when it failed. Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
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Lin Huang authored
AUX errors are caused by many different reasons. We may not know what happened in aux channel on failure, so let's reset aux channel if some errors occurred. Cc: 征增 王 <wzz@rock-chips.com> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
Lin Huang <hl@rock-chips.com> Signed-off-by:
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zain wang authored
There are some different bits between Rockchip and Exynos in register "AUX_PD". This patch fixes the incorrect operations about it. Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Lin Huang authored
We need to check the dpcd write/read return value to see whether the write/read was successful Cc: Kristian H. Kristensen <hoegsberg@chromium.org> Signed-off-by:
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zain wang authored
Enhanced mode is required by the eDP 1.2 specification, and not doing it early could result in a period of time where we have a link transmitting idle packets without it. Since there is no reason to disable it, we just enable it at the beginning of link training and then keep it on all the time. Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by:
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Lin Huang authored
There was a 1ms delay to detect the hpd signal, which is too short to detect a short pulse. This patch extends this delay to 100ms. Cc: Stéphane Marchesin <marcheu@chromium.org> Cc: 征增 王 <wzz@rock-chips.com> Signed-off-by:
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Lin Huang authored
When panel is shut down, we should make sure edp can be disabled to avoid undefined behavior. Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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zain wang authored
Following the correct power up sequence: dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00 Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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zain wang authored
According to DP spec v1.3 chap 3.5.1.2 Link Training, Link Policy Maker must first detect that the HPD signal is asserted high by the Downstream Device before establishing a link with it. Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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zain wang authored
When we enable bridge failed, we have to retry it, otherwise we would get the abnormal display. Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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zain wang authored
Panel would reset its setting when it powers down. It would forget the last succeeded link training setting. So we can't use the last successful link training setting to do fast link training. Let's reset fast_train_enable in analogix_dp_bridge_disable(); Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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Lin Huang authored
We should check AUX_EN bit to confirm the AUX CH operation is completed. Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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Lin Huang authored
We need to enable video before analogix_dp_is_video_stream_on(), so we can get the right video stream status. We needed to increase the delay in the timeout loop because there is random "Timeout of video streamclk ok" message happen when debug edp panel, this time do not define in the spec. Cc: 征增 王 <wzz@rock-chips.com> Cc: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
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- 23 Apr, 2018 7 commits
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Stefan Schake authored
Now that we set the OLED* registers to do CTM, it's helpful to have them in the register dump. Signed-off-by:
Stefan Schake <stschake@gmail.com> Signed-off-by:
Eric Anholt <eric@anholt.net> Reviewed-by:
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Stefan Schake authored
The hardware has a single block for applying a CTM prior to gamma lut. It can be fed with pixels from one of our CRTC at a time and uses a matrix with S0.9 scalars. Use private atomic state to reject attempts from userland to apply CTM for more than one CRTC at a time and reject matrices with scalars that we can't approximate without integer bits. Signed-off-by:
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Stefan Schake authored
The HVS supports mixing fixed alpha with per-pixel alpha or setting a fixed plane alpha in case there is no per-pixel information. This allows us to support the generic DRM plane alpha property. Signed-off-by:
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Wolfram Sang authored
We should get drvdata from struct device directly. Going via platform_device is an unneeded step back and forth. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Boris Brezillon authored
Document the bindings used for the Cadence DSI bridge. Signed-off-by:
Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180421070846.10330-2-boris.brezillon@bootlin.com
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Boris Brezillon authored
Add a driver for Cadence DPI -> DSI bridge. This driver only support a subset of Cadence DSI bridge capabilities. This driver has been tested/debugged in a simulated environment which explains why some of the features are missing. Here is a non-exhaustive list of missing features: * burst mode * DPHY init/configuration steps * support for additional input interfaces (SDI input) DSI commands and non-burst video mode have been tested. Signed-off-by:
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Fabio Estevam authored
platform_driver does not need to set the owner field, as this will be populated by the driver core. Generated by scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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- 20 Apr, 2018 2 commits
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Jacopo Mondi authored
Add DRM bridge driver for Thine THC63LVD1024 LVDS to digital parallel output converter. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by:
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Jacopo Mondi authored
Document Thine THC63LVD1024 LVDS decoder device tree bindings. Signed-off-by:
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