- 31 Jul, 2018 4 commits
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Rex Zhu authored
This test was reversed so it would end up leading to vddnb value can't be read via hwmon on APU. Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
the voltage showed in debugfs and hwmon should be in mV Reviewed-by:
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Rex Zhu authored
Only delete the dead temp variables in Polaris. Reviewed-by:
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Rex Zhu authored
DIDTConfig_Polaris12[] table missed a big chunk of data. Pointed by aidan.fabius <aidan.fabius@coreavi.com> Reviewed-by:
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- 27 Jul, 2018 19 commits
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Huang Rui authored
This patch cleans up spaces and align the text to refine the comment for amdgpu_ttm. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Junwei Zhang authored
pass the evict flag instead of hard code Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Bas Nieuwenhuizen authored
Every set_pages_array_wb call resulted in cross-core interrupts and TLB flushes. Merge more of them for less overhead. This reduces the time needed to free a 1.6 GiB GTT WC buffer as part of Vulkan CTS from ~2 sec to < 0.25 sec. (Allocation still takes more than 2 sec though) (v2): use set_pages_wb instead of set_memory_wb. Signed-off-by:
Bas Nieuwenhuizen <basni@chromium.org> Signed-off-by:
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Huang Rui authored
All non-x86 definitions are moved to ttm_set_memory header, so remove it from ttm_page_alloc.c. Suggested-by:
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Huang Rui authored
All non-x86 definitions are moved to ttm_set_memory header, so remove it from ttm_page_alloc_dma.c. Suggested-by:
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Huang Rui authored
This patch moves all non-x86 abstraction to the ttm_set_memory header. It is to make function calling more clearly. (v2): add ttm_ prefix. Suggested-by:
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Alex Deucher authored
Properly handle cases where one or more instance of the IP block may be harvested. v2: make sure ip_num_rings is initialized amdgpu_queue_mgr.c v3: rebase on Christian's UVD changes, drop unused var Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Harry Wentland authored
This structure needs to align with structure in atomfirmware table. Update it. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by:
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Harry Wentland authored
Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Anthony Koo authored
[Why] PSR_SET command is sent to the microcontroller in order to initialize parameters needed for PSR feature, such as telling the microcontroller which pipe is driving the PSR supported panel. When this command is skipped or fails, the microcontroller may program the wrong thing if driver tries to enable PSR. [How] If PSR_SET fails, do not set psr_enable flag to indicate the feature is not yet initialized. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
[Why] The sequence is slightly changed when bring .set_bandwidth out from the end of programming backend to the end of programming surface. Vega10 doesn't like to get clocks updated if stream_count is zero in the current context (Atomic Reset). [How] Do not update clocks if no stream is showing up in the context. Fixes 1b2b130192 "dc: Remove 300Mhz minimum disp clk limit." Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Bhawanpreet Lakha authored
[Why] engine and aux_engine are unnecessary layers we want to remove this layer. [How] flatten engine and aux engine structs into one struct called aux_engine and remove all references to the engine struct. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] Some receivers seem to fail the first link training but are good on subsequent tries. We want to retry link training again. This fixes HTC vive pro not lighting up after being disabled. [How] Check if the link training passed without fall back if this is not the case then we retry link training. Signed-off-by:
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Christian König authored
Patch the IBs for the second UVD instance so that userspace don't need to care about the instance they submit to. v2: use direct IB patching Signed-off-by:
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Christian König authored
We are going to need that for the second UVD instance on Vega20. v2: rename to patch_cs_in_place Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Updates for 4.19. Mostly bug fixes and cleanups. Highlights: - Internal API cleanup in GPU scheduler - Decouple i2c and aux abstractions in DC - Update maintainers - Misc cleanups - Misc bug fixes Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180725215326.2709-1-alexander.deucher@amd.com
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Dave Airlie authored
Merge tag 'exynos-drm-next-for-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next Cleanups - Change g2d driver to component based driver . g2d driver was last customed sub driver so this patch series changes it to component based driver, which also makes gem handling to be more simplify. - Cleanup of Exynos DRM suspend/resume . Register exynos drm core suspend/resume functions to prepare/complete callbacks of dev_pm_ops instead of suspend/resume callbacks to ensure exynos_drm_suspend() is called before any suspend callback from the real devices to avoid some issues on boards with complex pipelines. . Also Add pm_runtime_furce_suspend/resume as SYSTEM_SLEEP_PM_OPS to ensure that resources of each devices will be released for the system PM suspend/resume cycle. - Remove local value not used. Signed-off-by:
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git://linux-arm.org/linux-ldDave Airlie authored
I have a couple of small patches for malidp to be applied in drm-next. They have arisen from the decision to switch the writeback connectors to always connected. Signed-off-by:
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git://git.pengutronix.de/git/pza/linuxDave Airlie authored
drm/imx: cleanup and csi improvements - Remove the unused struct imx_drm_crtc and the unused pipes field from imx_drm_device and replace drm_dev_unref with drm_dev_put. - Extend CSI configuration to support RGB888 and BGR888 capture, as well as 16-bit RGB565 capture via a parallel bus. - Add CPMEM support for negative interlace offsets, which is necessary to support writing captured bottom-top interlaced fields to memory with interleaved lines. Signed-off-by:
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- 25 Jul, 2018 11 commits
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Jia-Ju Bai authored
cik_pcie_gen3_enable() is only called by cik_common_hw_init(), which is never called in atomic context. cik_pcie_gen3_enable() calls mdelay() to busily wait, which is not necessary. mdelay() can be replaced with msleep(). This is found by a static analysis tool named DCNS written by myself. Signed-off-by:
Jia-Ju Bai <baijiaju1990@gmail.com> Signed-off-by:
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Alex Deucher authored
The address printed is the actual address, not the page. Reviewed-by:
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Nayan Deshmukh authored
The scheduler of the entity is decided by the run queue on which it is queued. This patch avoids us the effort required to maintain a sync between rq and sched field when we start shifting entites among different rqs. Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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Nayan Deshmukh authored
entity has a scheduler field and we don't need the sched argument in any of the functions where entity is provided. Signed-off-by:
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Christian König authored
Make struct amdgpu_bo a bit smaller. Signed-off-by:
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Christian König authored
Just rename functions, no functional change. Signed-off-by:
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Christian König authored
Add separate entry for the power managent code on AMD GPUs. Signed-off-by:
Rex Zhu <rezhu@amd.com> Reviewed-by:
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Christian König authored
Note that Harry and Leo Li are maintainers for that stuff. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Christian König authored
Roger unfortunately doesn't work for AMD any longer. So add Rui and Jerry as co-maintainer as well. Signed-off-by:
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Christian König authored
Going to completely rework the context to ring mapping with Nayan's GSoC work, but for now just stopping to expose the second UVD instance should do it. Signed-off-by:
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Christian König authored
No need to bitcast a boolean and even if we should use "!!" instead. Signed-off-by:
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- 24 Jul, 2018 6 commits
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Harry Wentland authored
Signed-off-by:
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Jun Lei authored
[why] confusing as to which part of debug is informational, and which part causes behavioral change Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] Aux engine is created from i2caux layer. We want to remove this layer and use the engine directly. [How] Decouple aux engine from i2caux. Move aux engine related code to dce folder and use dc resource pool to manage the engine. And use the engine functions directly Signed-off-by:
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vikrant mhaske authored
[why] Diags has POR to run the video workload using AYCRCB8888 through DCN; capture it through DWB and send it to VCN hardware to encode [how] added the code to support this format so that DPP ICSC will be able to convert it from YUV444 to internal RGB and DWB OCSC will be able to convert from internal RGB to YUV420 Signed-off-by:
vikrant mhaske <vikrant.mhaske@amd.com> Reviewed-by:
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David Francis authored
[Why] When a dce100 asic was suspended, the clocks were not set to 0. Upon resume, the new clock was compared to the existing clock, they were found to be the same, and so the clock was not set. This resulted in a pernicious blackscreen. [How] In atomic commit, check to see if there are any active pipes. If no, set clocks to 0 Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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Tony Cheng authored
[why] diag specify what the full config and is only concerned about pass/fail at the end having inter-op code like verifiying we can actually train at reported link rate slows down diag test and add complexity we don't need [how] add dc_debug option to skip capability link trianing also remove hbr in function name as verify is not specific to hbr Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Acked-by:
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