- 31 Mar, 2014 39 commits
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Paul Burton authored
The CM registers use native endianness, so using plain readl & writel will produce incorrect results on big endian systems. Reported-by:
Jeffrey Deans <jeffrey.deans@imgtec.com> Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6656/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The gic_send_ipi_mask function declared in smp-ops.h takes a struct cpumask argument, but linux/cpumask.h is only included within an #ifdef CONFIG_SMP. Move the gic_ function declarations within that #ifdef too to fix warnings during build such as: In file included from arch/mips/fw/arc/init.c:15:0: /mnt/buildbot/kernel/mips/slave/mips-linux__allno_/build/arch/mips/include/asm/smp-ops.h:62:44: warning: 'struct cpumask' declared inside parameter list [enabled by default] extern void gic_send_ipi_mask(const struct cpumask *mask, unsigned int action); Reported-by:
Markos Chandras <markos.chandras@imgtec.com> Signed-off-by:
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Paul Burton authored
It's perfectly valid to use SMP on a non-MT CPU and use the GIC for IPIs. Set them up conditional upon CONFIG_MIPS_GIC_IPI rather than CONFIG_MIPS_MT_SMP. Signed-off-by:
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Paul Burton authored
Rather than duplicating the GIC IPI send function, share the one already used by CONFIG_MIPS_CPS & CONFIG_MIPS_CMP. Signed-off-by:
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Paul Burton authored
This probing is already done by decode_configs as part of cpu_probe, and furthermore the implementation here was incorrect for any MT core with a number of VPEs other than 2. Signed-off-by:
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Ralf Baechle authored
With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III mode through .set mips3 results in *lots* of warnings like {standard input}: Assembler messages: {standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension during a kernel build. Fixed by using .set arch=r4000 instead. This breaks support for building the kernel with binutils 2.13 which was supported for 32 bit kernels only anyway and 2.14 which was a bad vintage for MIPS anyway. Signed-off-by: -
Paul Burton authored
In cores which implement the MT ASE, the CPUNum in the EBase register is a concatenation of the core number & the VPE ID within that core. In order to retrieve the correct core number CPUNum must be shifted appropriately to remove the VPE ID bits. Signed-off-by:
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Paul Burton authored
This function simply returns the number of VPEs present in the current core, or 1 if the core does not implement the MT ASE. In SMP kernels this will typically equal smp_num_siblings, however it will also be usable in UP kernels and helps prepare for the possibility of a heterogenous system where the VPE count is not the same across all cores. Signed-off-by:
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Paul Burton authored
Both the CONFIG_MIPS_CPS & CONFIG_MIPS_CMP SMP implementations call mips_mt_set_cpuoptions when preparing to start secondary CPUs. However both may be used without MT. Provide an empty inline function to prevent a link error in this case. Signed-off-by:
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Julia Lawall authored
Use del_timer_sync to ensure that the timer is stopped on all CPUs before the driver exists. This change was suggested by Thomas Gleixner The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r@ declarer name module_exit; identifier ex; @@ module_exit(ex); @@ identifier r.ex; @@ ex(...) { <... - del_timer + del_timer_sync (...) ...> } // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Cc: kernel-janitors@vger.kernel.org Cc: tglx@linutronix.de Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6663/Signed-off-by:
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Paul Burton authored
This patch ensures that the kernel sets a sane base address for the PIIX4 PM I/O register region during boot. Without this the kernel may not successfully claim the region as a resource if the bootloader didn't configure the region. With this patch the kernel will always succeed with: pci 0000:00:0a.3: quirk: [io 0x1000-0x103f] claimed by PIIX4 ACPI The lack of the resource claiming is easily reproducible without this patch using current versions of QEMU. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6641/Signed-off-by:
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Huacai Chen authored
Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
Hongliang Tao <taohl@lemote.com> Signed-off-by:
Hua Yan <yanh@lemote.com> Tested-by:
Alex Smith <alex.smith@imgtec.com> Reviewed-by:
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Huacai Chen authored
Tips of Loongson's CPU hotplug: 1, To fully shutdown a core in Loongson 3, the target core should go to CKSEG1 and flush all L1 cache entries at first. Then, another core (usually Core 0) can safely disable the clock of the target core. So play_dead() call loongson3_play_dead() via CKSEG1 (both uncached and unmmaped). 2, The default clocksource of Loongson is MIPS. Since clock source is a global device, timekeeping need the CP0' Count registers of each core be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI to ask Core-0's Count. Signed-off-by:
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Huacai Chen authored
IPI registers of Loongson-3 include IPI_SET, IPI_CLEAR, IPI_STATUS, IPI_EN and IPI_MAILBOX_BUF. Each bit of IPI_STATUS indicate a type of IPI and IPI_EN indicate whether the IPI is enabled. The sender write 1 to IPI_SET bits generate IPIs in IPI_STATUS, and receiver write 1 to bits of IPI_CLEAR to clear IPIs. IPI_MAILBOX_BUF are used to deliver more information about IPIs. Why we change code in arch/mips/loongson/common/setup.c? If without this change, when SMP configured, system cannot boot since it hang at printk() in cgroup_init_early(). The root cause is: console_trylock() \-->down_trylock(&console_sem) \-->raw_spin_unlock_irqrestore(&sem->lock, flags) \-->_raw_spin_unlock_irqrestore()(SMP/UP have different versions) \-->__raw_spin_unlock_irqrestore() (following is the SMP case) \-->do_raw_spin_unlock() \-->arch_spin_unlock() \-->nudge_writes() \-->mb() \-->wbflush() \-->__wbflush() In previous code __wbflush() is initialized in plat_mem_setup(), but cgroup_init_early() is called before plat_mem_setup(). Therefore, In this patch we make changes to avoid boot failure. Signed-off-by: -
Huacai Chen authored
Added Kconfig options include: Loongson-3 CPU and machine definition, CPU cache features, UEFI-like firmware interface (LEFI), HT-linked PCI, and swiotlb support. Signed-off-by:
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Huacai Chen authored
Loongson doesn't support DMA address above 4GB traditionally. If memory is more than 4GB, CONFIG_SWIOTLB and ZONE_DMA32 should be selected. In this way, DMA pages are allocated below 4GB preferably. However, if low memory is not enough, high pages are allocated and swiotlb is used for bouncing. Moreover, we provide a platform-specific dma_map_ops::set_dma_mask() to set a device's dma_mask and coherent_dma_mask. We use these masks to distinguishes an allocated page can be used for DMA directly, or need swiotlb to bounce. Recently, we found that 32-bit DMA isn't a hardware bug, but a hardware configuration issue. So, latest firmware has enable the DMA support as high as 40-bit. To support all-memory DMA for all devices (besides the Loongson platform limit, there are still some devices have their own DMA32 limit), and also to be compatible with old firmware, we keep use swiotlb. Signed-off-by:
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Huacai Chen authored
Loongson family machines has three types of serial port: PCI UART, LPC UART and CPU internal UART. Loongson-2E and parts of Loongson-2F based machines use PCI UART; most Loongson-2F based machines use LPC UART; Loongson-2G/3A has both LPC and CPU UART but usually use CPU UART. Port address of UARTs: CPU UART: REG_BASE + OFFSET; LPC UART: LIO1_BASE + OFFSET; PCI UART: PCIIO_BASE + OFFSET. Since LPC UART are linked in "Local Bus", both CPU UART and LPC UART are called "CPU provided serial port". Signed-off-by:
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Huacai Chen authored
IRQ routing path of Loongson-3: Devices(most) --> I8259 --> HT Controller --> IRQ Routing Table --> CPU ^ | Device(legacy devices such as UART) --> Bonito ---| IRQ Routing Table route 32 INTs to CPU's INT0~INT3(IP2~IP5 of CP0), 32 INTs include 16 HT INTs(mostly), 4 PCI INTs, 1 LPC INT, etc. IP6 is used for IPI and IP7 is used for internal MIPS timer. LOONGSON_INT_ROUTER_* are IRQ Routing Table registers. I8259 IRQs are 1:1 mapped to HT1 INTs. LOONGSON_HT1_* are configuration registers of HT1 controller. Signed-off-by: -
Huacai Chen authored
Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With LEFI firmware interface, We don't need fixup for PCI irq routing (except providing a VBIOS of the integrated GPU). Signed-off-by:
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Huacai Chen authored
The new UEFI-like firmware interface (LEFI, i.e. Loongson Unified Firmware Interface) has 3 advantages: 1, Firmware export a physical memory map which is similar to X86's E820 map, so prom_init_memory() will be more elegant that #ifdef clauses can be removed. 2, Firmware export a pci irq routing table, we no longer need pci irq routing fixup in kernel's code. 3, Firmware has a built-in vga bios, and its address is exported, the linux kernel no longer need an embedded blob. With the LEFI interface, Loongson-3A/2G and all their successors can use a unified kernel. All Loongson-based machines support this new interface except 2E/2F series. Signed-off-by:
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Huacai Chen authored
Add four Loongson-3 based machine types: MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops; MACH_LEMOTE_A1101 is mini-itx; MACH_LEMOTE_A1205 is all-in-one machine. The most significant differrent between A1004/A1201 and A1101/A1205 is the laptops have EC but others don't. Signed-off-by:
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Huacai Chen authored
Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by:
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Huacai Chen authored
Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2 fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2. Loongson-3 has a hardware-maintained cache, system software doesn't need to maintain coherency. Loongson-3A is the first revision of Loongson-3, and it is the quad- core version of Loongson-2G. Loongson-3A has a simplified version named Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two HyperTransport controller but 2Gq has only one. HT0 is used for cross- chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq cannot support NUMA but 3A can. For software, Loongson-2Gq is simply identified as Loongson-3A. Exsisting Loongson family CPUs: Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs. Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit single-core MIPS CPUs. Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are 64-bit multi-core MIPS CPUs. Signed-off-by: -
Ralf Baechle authored
And there are more CPUs or configurations that want to provide special per-CPU information in /proc/cpuinfo. So I think there needs to be a hook mechanism, such as a notifier. This is a first cut only; I need to think about what sort of looking the notifier needs to have. But I'd appreciate testing on MT hardware! Signed-off-by:
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Rafał Miłecki authored
Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/6627/Signed-off-by:
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Linus Walleij authored
When an IRQ is started on a GPIO line, mark this GPIO as IRQ in the gpiolib so we can keep track of the usage centrally. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Cc: Alexandre Courbot <acourbot@nvidia.com> Patchwork: https://patchwork.linux-mips.org/patch/6417/Signed-off-by:
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Paul Burton authored
All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by:
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Paul Burton authored
All architecturally defined bits in the FPU implementation register are read only & unchanging. It contains some implementation-defined bits but the architecture manual states "This bits are explicitly not intended to be used for mode control functions" which seems to provide justification for viewing the register as a whole as unchanging. This being the case we can simply re-use the value we read at boot rather than having to re-read it later, and avoid the complexity which that read entails. Signed-off-by:
Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6144/Signed-off-by:
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Wu Zhangjin authored
If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This may save about 10k for the compressed kernel image(vmlinuz). Signed-off-by:
Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1901/Signed-off-by:
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Daniel Walker authored
This adds an ad-hoc error injection method. Octeon II doesn't have hardware support for injection, so this simulates it. Signed-off-by:
Daniel Walker <dwalker@fifo99.com> Cc: David Daney <david.daney@cavium.com> Cc: Doug Thompson <dougthompson@xmission.com> Cc: linux-edac@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5873/Signed-off-by:
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Daniel Walker authored
If the opstate_init() isn't called the driver won't start properly. I just added it in what appears to be an appropriate place. Signed-off-by:
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Richard Weinberger authored
The symbol is an orphan, get rid of it. Signed-off-by:
Richard Weinberger <richard@nod.at> Cc: linux-mips@linux-mips.org (open list:MIPS) Cc: linux-kernel@vger.kernel.org (open list) Patchwork: https://patchwork.linux-mips.org/patch/6523/Signed-off-by:
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Paul Gortmaker authored
The sead3-mtd.o is built for obj-y -- and hence this code is always present. It will never be modular, so using module_init as an alias for __initcall can be somewhat misleading. Fix this up now, so that we can relocate module_init from init.h into module.h in the future. If we don't do this, we'd have to add module.h to obviously non-modular code, and that would be a worse thing. Note that direct use of __initcall is discouraged, vs. one of the priority categorized subgroups. As __initcall gets mapped onto device_initcall, our use of device_initcall directly in this change means that the runtime impact is zero -- it will remain at level 6 in initcall ordering. We also fix a missing semicolon, which this change uncovers. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Reported-by:
kbuild test robot <fengguang.wu@intel.com> Cc: linux-mips@linux-mips.org Cc: fengguang.wu@intel.com Patchwork: https://patchwork.linux-mips.org/patch/6412/Signed-off-by:
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Ralf Baechle authored
Don't depend on CONFIG_IDE to make this more robust. Signed-off-by: -
Huacai Chen authored
Loongson-1 is a 32-bit MIPS CPU and Loongson-2/3 are 64-bit MIPS CPUs, and both Loongson-2/3 has the same PRID IMP filed (0x6300). As a result, renaming PRID_IMP_LOONGSON1 and PRID_IMP_LOONGSON2 to PRID_IMP_LOONGSON_32 and PRID_IMP_LOONGSON_64 will make more sense. Signed-off-by:
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Paul Bolle authored
Commit c24a8a7a ("MIPS: Netlogic: Add MSI support for XLP") added "select ARCH_SUPPORTS_MSI". But the Kconfig symbol ARCH_SUPPORTS_MSI was already removed in v3.12, so that select is a nop. Drop it. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Cc: Jayachandran C <jchandra@broadcom.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6521/Signed-off-by:
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Deng-Cheng Zhu authored
Choose event/cache maps and handle raw event mapping for interAptiv. Update code comments. Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by:
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Deng-Cheng Zhu authored
Choose event/cache maps and handle raw event mapping for proAptiv. Update code comments. Signed-off-by:
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Deng-Cheng Zhu authored
74K/proAptiv share the same event/cache maps. So it's better to change the names of the existing mipsxx74Kcore_[event|cache]_map. Signed-off-by:
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- 26 Mar, 2014 1 commit
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Jingoo Han authored
The HAVE_PWM symbol is only for legacy platforms that provide the PWM API without using the generic framework. The jz4740 platform uses the generic PWM framework, after the commit "f6b8a570 pwm: Add Ingenic JZ4740 support". Signed-off-by:
Jingoo Han <jg1.han@samsung.com> Acked-by:
Lars-Peter Clausen <lars@metafoo.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6525/Signed-off-by:
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