- 15 May, 2004 5 commits
-
-
Robin Farine authored
Patch from Robin Farine Fix the xscale cache handling routines that were invalidating a D cache line instead of draining the write & fill buffer as intended.
-
Catalin Marinas authored
Patch from Catalin Marinas Unlike the v5 architecture, the ARM1136 requires that BIT4 is 0 in the first level page descriptor (ARM1136 TRM, page 6-39). It works at the moment but it might break future v6 cores.
-
Catalin Marinas authored
Patch from Catalin Marinas The v6_dma_invalidate_range - the "mcr" instruction for draining the write buffer requires r0 == 0. A "cmp" instruction for testing the end address is missing in the v6_dma_flush_range function.
-
Catalin Marinas authored
Patch from Catalin Marinas The _raw_write_(try)lock functions in include/asm-arm/spinlock.h should use the early clobber modifier (&) for the "tmp" register. A newer compiler (gcc-3.4.0) generates an "strexeq %0, %1, [%2]" instruction where %0 is the same as %2, which is illegal.
-
Catalin Marinas authored
Patch from Catalin Marinas In the blockops_check() function, cache_type is uninitialised because an "mcr" instruction is used instead of "mrc".
-
- 13 May, 2004 18 commits
-
-
bk://dsaxena.bkbits.net/linux-2.6-for-rmkRussell King authored
into flint.arm.linux.org.uk:/usr/src/bk/linux-2.6-rmk
-
Ben Dooks authored
Patch from Ben Dooks Removed two 's from assembly code (binutils has problems with these)
-
Ben Dooks authored
Patch from Ben Dooks Initial support for SMDK2410 and variants
-
Ben Dooks authored
Patch from Ben Dooks Fix selection configuration entry for UART number for low-level debug
-
John Lenz authored
Patch from John Lenz Add the sa1100fb_mach_info structure for collie
-
bk://dsaxena.bkbits.net/linux-2.6-for-rmkRussell King authored
into flint.arm.linux.org.uk:/usr/src/bk/linux-2.6-ds
-
Nicolas Pitre authored
Patch from Nicolas Pitre On the PXA27x it's also possible to get the IRQ info from CP6 and it has a much lower latency than the memory mapped equivalent.
-
Nicolas Pitre authored
Patch from Nicolas Pitre
-
Nicolas Pitre authored
Patch from Nicolas Pitre
-
Nicolas Pitre authored
Patch from Nicolas Pitre This reworks PXA register mapping to accommodate the extra registers of the PXA27x chips (aka Bulverde).
-
Nicolas Pitre authored
Patch from Nicolas Pitre
-
John K. Luebs authored
Patch from John K Luebs This adds support to preserve the GPIO level across a suspend and resume for PXA machine types. Removes the hack to preserve the FFUART state as this is unnecessary with the 2.6 serial driver code.
-
Tony Lindgren authored
Patch from Tony Lindgren Removes old duplicate board specific files that have been renamed to board-*.c
-
Tony Lindgren authored
Patch from Tony Lindgren Changes OMAP low level debug function to allow virtual IO != physical IO. Also removes waituart checking, as it only worked for first serial port.
-
Ian Campbell authored
Patch from Ian Campbell The patch includes the PXA FB driver discussed recently on the arm-kernel mailing list, I have incorporated your (RMK's) comments from patch 1826.
-
Deepak Saxena authored
Add INIT_MACHINE() to ixp4xx platform setup code
-
Deepak Saxena authored
Remove unused flag variable from ixp4xx_timer_interrupt
-
Deepak Saxena authored
new file
-
- 12 May, 2004 6 commits
-
-
Deepak Saxena authored
IXP4xx support
-
Deepak Saxena authored
-
Deepak Saxena authored
IXP4xx support
-
Deepak Saxena authored
IXP4xx support
-
Deepak Saxena authored
IXP4xx support
-
Deepak Saxena authored
IXP4xx family of network processors. The code still needs some cleanup here and there, but it's to the point that it's should be OK to push upstream. Some of the remaining TODOs: - Cleanup GPIO IRQ handling for edge-trigered HW (none exists ATM) - Add IDE driver for various platforms - Misc cleanups This patch adds the changes to arch/arm/Makefile and arch/arm/Kconfig
-
- 11 May, 2004 1 commit
-
-
Geert Uytterhoeven authored
M68k: Remove superfluous whitespace that hurts my eyes with `let c_space_errors=1' in vim. This includes correcting trailing whitespace and spaces in front of tabs. `diff -urNbB' shows no difference before/after.
-
- 10 May, 2004 10 commits
-
-
Jeff Garzik authored
In MAINTAINERS and in individual low-level drivers.
-
Jeff Garzik authored
* bug fix: make sure 'nsect' member of struct ata_queued_cmd is initialized each time a cmd is re-used. Only affects PIO data xfers, which nobody uses. * slightly change the way a device's flags are printed out. currently the only flag is 'lba48', but soon 'wcache' will appear also. * add WB-cache-related constants and macros to linux/ata.h
-
David Eger authored
This fixes a corruption problem with overlapping copyarea()'s in the radeon driver.
-
Paul Mackerras authored
At the moment, on PPC64, the instruction we use for wmb() doesn't order cacheable stores vs. non-cacheable stores. (It does order cacheable vs. cacheable and non-cacheable vs. non-cacheable.) This causes problems in the sort of driver code that writes stuff into memory, does a wmb(), then a writel to the device to start a DMA operation to read the stuff it has just written to memory. This patch solves the problem by adding a sync instruction before the store in the write* and out* macros. The sync is a full barrier that orders all loads and stores, cacheable or not. The patch also moves the eieio instruction that we had after the store to before the load in the read* and in* macros. With the sync before the store, we don't need an eieio as well in a sequence of stores, but we still need an eieio between a store and a load. I think it is better to do this than to turn wmb() into a full memory barrier (a sync instruction) because the full barrier is slow and isn't needed with the sync in the write*/out* macros. This way, write*/out* are fully ordered with respect to preceding loads and stores, which is what driver writers expect, and we avoid penalizing users of wmb() who are only doing cacheable stores.
-
-
Matthew Wilcox authored
- Split PA7300LC from PA7100LC (Matthew Wilcox) - Handle 32-bit firmware and 64-bit kernel at runtime (Ryan Bradetich) - Fix building in a separate tree (Matthew Wilcox) - Update defconfigs (Randolph Chung) - Make WCHAN work (Randolph Chung) - Initial support for SMP in 2.6 (Grant Grundler) - Use 8-byte PTEs on 32-bit kernels (James Bottomley) - Implement L2/L3 hybrid page tables for 64 bit kernels (James Bottomley) - Support 8TB of physical and virtual address space (James Bottomley) - Macro'ise the tlb miss handlers (James Bottomley) - Check the ptrace flags correctly in the syscall return path (Randolph Chung) - Eliminate many magic numbers (James Bottomley) - Work around linker bug in vmlinux.lds.S (James Bottomley) - Many cache flushing fixes (James Bottomley) - first baby step for PA8800 support (Grant Grundler) - Self-aligning spinlocks (Randolph Chung)
-
Geert Uytterhoeven authored
M68k: <asm/virtconvert.h> needs include <linux/compiler.h> for __attribute_const__ (from Richard Zidlicky)
-
Geert Uytterhoeven authored
Sun3x: Like most other platforms, Sun3x needs conswitchp set if CONFIG_DUMMY_CONSOLE is defined (from Sam Creasey)
-
bk://gkernel.bkbits.net/libata-2.6Linus Torvalds authored
into ppc970.osdl.org:/home/torvalds/v2.6/linux
-
bk://gkernel.bkbits.net/net-drivers-2.6Linus Torvalds authored
into ppc970.osdl.org:/home/torvalds/v2.6/linux
-