- 26 Sep, 2017 40 commits
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eric Cook authored
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Eric <eric.cook@amd.com> Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Ding Wang authored
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Ding Wang <Ding.Wang@amd.com> Acked-by:
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Eric Cook authored
-check for min/max range in freesync calculation and handle it accordingly Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Ding Wang authored
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Tony Cheng authored
to avoid null access in case res_ctx is used to access res_pool before it's fully constructed also make it clear which function has dependency on resource_pool Signed-off-by:
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Eric Cook authored
Implement core support to allow for FreeSync Auto Sweep to work Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Tony Cheng authored
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Tony Cheng authored
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Sylvia Tsai authored
- Refacotr PSR to follow correct module pattern - fix eDP only working on sink index 0. Signed-off-by:
Sylvia Tsai <sylvia.tsai@amd.com> Acked-by:
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Zeyu Fan authored
Signed-off-by:
Zeyu Fan <Zeyu.Fan@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This change will cache cursor attributes and reprogram them when enabling cursor after power gating if the attributes were not yet reprogrammed Signed-off-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Acked-by:
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Yongqiang Sun authored
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Amy Zhang authored
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Amy Zhang <Amy.Zhang@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Yongqiang Sun authored
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Dmytro Laktyushkin authored
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Harry Wentland authored
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Zeyu Fan authored
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Shirish S authored
dc_commit_surfaces_to_stream() function currently is handle's only one plane at a time. This will not work if multiple planes have to be set to a crtc. The functionality of dc_commit_surfaces_to_stream() with this patch is slit into 1. Accumulate and initialise all the surfaces that needs to be set to a crtc. 2. Update the intialised set of surfaces to the steam in one go. Hence dc_commit_surfaces_to_stream() is renamed to init_surfaces(). Once all the planes requested by user space are initialised, dc_commit_surfaces_to_stream() shall sequentially populates *updates, *flip_addr, *plane_info and *scaling_info for all surfaces. BUG: SWDEV-119421 TEST: (On Chromium OS for Stoney Only) * Chromium UI comes up, on both eDP & DP. * 'new_surface_count' now changes as per user input for e.g for all below run tests its 2, without this patch for the below tests it used to be 1 * Executed below tests to see YUV(underlay) & RGB planes on eDP plane_test --format XR24 --size 500x100 -p --format YV12 --size 500x500 plane_test --format AR24 --size 500x50 -p --format YV12 --size 150x150 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768 Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Shirish S authored
This patch updates the planes default offsets to the appropriate ones, and aligns the pitch to 64 bits. BUG=SWDEV-119421 TEST=Boots to UI on jadeite TEST= plane_test --format AR24 --size 500x50 -p --format YV12 --size 500x500 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1280x720 plane_test --format AR24 --size 500x50 -p --format YV12 --size 1366x768 Signed-off-by: -
Shirish S authored
This patch populates the YUV surface configurations. Tests: (On Chromium OS for Stoney Only) builds without any errors. Signed-off-by:
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Harry Wentland authored
This will allow us to carry it from check to commit Signed-off-by:
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Harry Wentland authored
This will be needed to clean up context once we add it to private atomic state. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
This should make things simpler when we try to rework this later when we pass validate_context from atomic_check to atomic_commit. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Signed-off-by:
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Harry Wentland authored
If we need to update our context we can allocate memory. No need to keep temporary memory for this. Signed-off-by:
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Harry Wentland authored
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Eric Cook authored
- Update BTR/LFC logic so that V_TOTAL_MIN/MAX will take affect on current frame - Add in FreeSync update to MPO code path Signed-off-by:
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Vitaly Prosyak authored
Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by:
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Sylvia Tsai authored
They could differ between ASIC generations Signed-off-by:
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Charlene Liu authored
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Jordan Lazare authored
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Ding Wang authored
- Set stream signal type to be SST when setting non-tile timing on MST tiled display. - Disable MST on sink after disabling MST link. - Enable MST on sink before enabling MST link. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Signed-off-by:
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