- 09 Aug, 2019 5 commits
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Jani Nikula authored
It used to be handy that we only had a couple of headers, but over time i915_drv.h has become unwieldy. Extract declarations to a separate header file corresponding to the implementation module, clarifying the modularity of the driver. Ensure the new header is self-contained, and do so with minimal further includes, using forward declarations as needed. Include the new header only where needed, and sort the modified include directives while at it and as needed. No functional changes. Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d7826e365695f691a3ac69a69ff6f2bbdb62700d.1565271681.git.jani.nikula@intel.com
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Jani Nikula authored
Seems like a better fit. Reduce clutter in i915_drv.[ch]. Reviewed-by:
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Jani Nikula authored
It's for display. Seems like a better fit. Reduce clutter in i915_drv.h. Reviewed-by:
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Jani Nikula authored
Seems like a better fit. Reduce clutter in i915_drv.h. Reviewed-by:
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Jani Nikula authored
The last user of dev_priv->no_aux_handshake was removed in commit 3cf2efb1 ("Revert "drm/i915/dp: use VBT provided eDP params if available""). Finally remove the leftovers. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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- 08 Aug, 2019 16 commits
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Chris Wilson authored
Currently we walk the entire list of obj->vma for each obj within a file to find the matching vma of this context. Since we know we are searching for a particular vma bound to a user context, we can use the rbtree to search for it rather than repeatedly walk everything. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190808162407.28121-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Skip printing out idle engines that did not contribute to the GPU hang. As the number of engines gets ever larger, we have increasing noise in the error state where typically there is only one guilty request on one engine that we need to inspect. Signed-off-by:
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Chris Wilson authored
As we need to acquire a mutex to serialise the final intel_wakeref_put, we need to ensure that we are in process context at that time. However, we want to allow operation on the intel_wakeref from inside timer and other hardirq context, which means that need to defer that final put to a workqueue. Inside the final wakeref puts, we are safe to operate in any context, as we are simply marking up the HW and state tracking for the potential sleep. It's only the serialisation with the potential sleeping getting that requires careful wait avoidance. This allows us to retain the immediate processing as before (we only need to sleep over the same races as the current mutex_lock). v2: Add a selftest to ensure we exercise the code while lockdep watches. v3: That test was extremely loud and complained about many things! v4: Not a whale! Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111295 References: https://bugs.freedesktop.org/show_bug.cgi?id=111245 References: https://bugs.freedesktop.org/show_bug.cgi?id=111256 Fixes: 18398904 ("drm/i915: Only recover active engines") Fixes: 51fbd8de ("drm/i915/pmu: Atomically acquire the gt_pm wakeref") Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190808202758.10453-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Grr, missed one*. For using the legacy engine map, we should use engine->legacy_idx. Ideally, we should know the intel_context in the selftest and avoid all the fiddling around with unwanted GEM contexts. * In my defence, the conflict was added in another patch after it was tested by CI. v2: mock engines needs legacy love as well Fixes: f1c4d157 ("drm/i915: Fix up the inverse mapping for default ctx->engines[]") Signed-off-by:
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José Roberto de Souza authored
On TGL this register do not map directly to port, it was already handled when setting it(TGL_TRANS_DDI_SELECT_PORT()) but not when reading it. To make it consisntent adding a macro for the older gens too. v2: Adding TGL_PORT_TRANS_DDI_SELECT() so all future users can reuse it (Lucas) v3: Missed parentheses arround val (Jose) v4: Renamed TGL_PORT_TRANS_DDI_SELECT to TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT (Lucas) Added TRANS_DDI_FUNC_CTL_VAL_TO_PORT (Lucas) Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190808004935.1787-2-jose.souza@intel.com
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José Roberto de Souza authored
When getting the pipes attached to encoder if it is not a eDP encoder it iterates over all pipes and read a transcoder register. But it should not read a transcoder register before get its power domain. It was not a issue in gens older than 12 because if it only had port A connected it would be attached to EDP and it would skip all the transcoders readout, if it had more than one port connected, pipe B would cause PG3 to be on and it contains all other transcoders. But on gen 12 there is no EDP transcoder so it is always iterating over all pipes and if only one sink is connected, PG3 is kept off and reading other transcoders registers would cause a unclaimed read warning. So here getting the power domain of the transcoder only if it is enabled, otherwise it is not connected to the DDI. Reviewed-by:
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Chris Wilson authored
The order in which we store the engines inside default_engines() for the legacy ctx->engines[] has to match the legacy I915_EXEC_RING selector mapping in execbuf::user_map. If we present VCS2 as being the second instance of the video engine, legacy userspace calls that I915_EXEC_BSD2 and so we need to insert it into the second video slot. v2: Record the legacy mapping (hopefully we can remove this need in the future) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111328 Fixes: 2edda80d ("drm/i915: Rename engines to match their user interface") Signed-off-by:
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Chris Wilson authored
Ignore the central i915->kernel_context for allocating an engine, as that GEM context is being phased out. For internal clients, we just need the per-engine logical state, so allocate it at the point of use. Signed-off-by:
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Chris Wilson authored
Modernise the mock_request factory to take intel_context not a (GEM context, intel_engine_cs) tuple. Signed-off-by:
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Vandita Kulkarni authored
Blanking packet bit will control whether the transcoder allows the link to enter the LP state during BLLP regions (assuming there is enough time), or whether it will keep the link in the HS state with a Blanking Packet Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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Vandita Kulkarni authored
Most of the functions and mipi dsi sequence remains same as of ICL for TGL. Hence extending the support to TGL. Signed-off-by:
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Vandita Kulkarni authored
For TGL, there is no need to keep DDI clock on till IO enabling for mipi dsi. Signed-off-by:
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Vandita Kulkarni authored
Do not override TA_SURE timing parameter to zero for DSI 8X frequency 800MHz or below on TGL. Signed-off-by:
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Vandita Kulkarni authored
Latency programming remains same as that of ICL and setting latency otimization for PCS_DW1 lanes is same as that of EHL, hence extending it to TGL. Signed-off-by:
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Vandita Kulkarni authored
Program vblank register for mipi dsi in video mode on TGL. Signed-off-by:
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Jani Nikula authored
Abstract the rather self-contained piece of code from i915_drv.[ch]. No functional changes. Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
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- 07 Aug, 2019 19 commits
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Michal Wajdeczko authored
Insert few more failure points into firmware fetch procedure to check use of the wrong blob name or use of the mismatched firmware versions. Also update some messages (remove ptr, duplicated infos) and stop treating all fetch errors as missing firmware case. v2: update log levels (Chris) Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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Michal Wajdeczko authored
WOPCM programming error might be due to inserted earlier probe failure that could affects HuC firmware loading and thus impacts result of WOPCM partitioning that would be now incompatible with previously programmed values. Signed-off-by:
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Michal Wajdeczko authored
No need to define it globally as we're only using it in wopcm.c Signed-off-by:
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Michal Wajdeczko authored
For meaningful WOPCM partitioning we need GuC (and optionally HuC) firmware size(s) and we shouldn't just rely on GuC support flag, as we might fail to fetch GuC firmware and it's size will be 0 and all calculations will be just wrong/useless. Signed-off-by:
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Michal Wajdeczko authored
When we failed to fetch GuC firmware there is no point in fetching HuC firmware as we will not be able to use it without working GuC. Signed-off-by:
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Michal Wajdeczko authored
There is no point in selecting HuC firmware if GuC is unsupported or it was already disabled, as we need GuC to authenticate HuC. While around, make uc_fw_init_early work without direct access to whole i915, pass only needed platform/rev info. Signed-off-by:
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Michal Wajdeczko authored
While modparams are global for the i915 module, we are reporting status of the params applied against specific device instance. Signed-off-by:
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Umesh Nerlige Ramappa authored
The oa object manages the oa buffer and must be allocated when the user intends to read performance counter snapshots. This can be achieved by making the oa object part of the stream object which is allocated when a stream is opened by the user. Attributes in the oa object that are gen-specific are moved to the perf object so that they can be initialized on driver load. The split provides a better separation of the objects used in perf implementation of i915 driver so that resources are allocated and initialized only when needed. v2: Fix checkpatch warnings v3: Addressed Lionel's review comment v4: Rebase v5: Fix rebase/merge issue with ratelimit_state_init Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by:
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Chris Wilson authored
This giant switch has tendrils all other the struct and does not fit in with the rest of the driver bring up and control in i915_drv.c. Push it to one side so that it can grow in peace. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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Chris Wilson authored
For forklifted frankenkernels, the reported kernel version has no bearing on the actual driver version. Include our own driver date that is updated every time we tag drm-intel-next. Signed-off-by:
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Dan Carpenter authored
There were several places which check for NULL when they should have been checking for IS_ERR(). Fixes: d8af05ff ("drm/i915: Allow sharing the idle-barrier from other kernel requests") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Chris Wilson authored
Use the same mechanism to determine if a backend engine exists for a uabi mapping as used internally. Signed-off-by:
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Chris Wilson authored
During engine setup, we may find that some engines are fused off causing a misalignment between internal names and the instances seen by users, e.g. (I915_ENGINE_CLASS_VIDEO_DECODE, 1) may be vcs2 in hardware. Normally this is invisible to the user, but a few debug interfaces (and our own internal tracing) use the original HW name not the name the user would expect as formed from their class:instance tuple. Replace our internal name with the uabi name for consistency with, for example, error states. v2: Keep the pretty printing of class name in the selftest Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111311Signed-off-by:
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Chris Wilson authored
We don't really want to use VM_IO for our GGTT mmaps (it implies that the mmap contains memory mapped registers, which we do not expose) yet I overzealously added it to an assert just because that's how we always had setup the vma. Signed-off-by:
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190807094128.9993-1-chris@chris-wilson.co.uk
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Rodrigo Vivi authored
Increase abstraction of display suspend/resume operations by providing higher level functions, and hiding the details inside intel_display_power.c. v2: Make checkpatch happy: - braces {} are not necessary for single statement blocks v3: Also move hsw/bdw PC8 sequences since they are related to display PM anyways. (Ville) v4: Rebase after a long time, plus Move functions to the new intel_display_power so we can stop exporting platform specific functions as pointed by Jani. v5: Remove unnecessary braces. v6 by Jani: make this purely non-functional cleanup, make functions static Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: -
Jani Nikula authored
Move the property enums closer to home. Acually make the broadcast macros an enum while at it. Reviewed-by:
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Jani Nikula authored
With its original name intel_drv.h the intel_display_types.h header was superfluously cargo-cult included all over the place, while it's really mostly about display internals. Remove the unnecessary includes. Reviewed-by:
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Jani Nikula authored
Everything about the file is about display, and mostly about types related to display. Move under display/ as intel_display_types.h to reflect the facts. There's still plenty to clean up, but start off with moving the file where it logically belongs and naming according to contents. v2: fix the include guard name in the renamed file Reviewed-by:
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Jani Nikula authored
Disentangle i915_drv.h from intel_drv.h, which gets included via i915_trace.h. This necessitates including i915_trace.h wherever it's needed. Reviewed-by:
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