- 03 Oct, 2012 40 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
v2: Ben Skeggs <bskeggs@redhat.com> - fill in nouveau_pm.dev to prevent oops - fix ppc issues (build + OF shadow) Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
v2: Ben Skeggs <bskeggs@redhat.com> - de-inline nv_icmd, triggers some gcc issue causing ctxnv[ce]0.c to take a *very* *very* long time to build on some configs. Signed-off-by: -
Ben Skeggs authored
This is all very much a policy thing, and hence will not belong in SW after the rework. engsw now only handles receiving the event to say "can flip now" and makes a callback to perform the actual work. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
There's a *lot* of code in here, and it's all going to use the PGRAPH priv pointer rather than drm_device after the engine rework. This is handling all the rename-only parts of the change. Signed-off-by: -
Ben Skeggs authored
Still the same code, but not an "engine" anymore. The fence code is more of a policy decision rather than exposing mechanisms, so it's not appropriate to port it to the new engine subsystem. Signed-off-by: -
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v2 (Ben Skeggs): - some fixes for 64KiB PAGE_SIZE - fix porting issues in (currently unused) nv41/nv44 pciegart code Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Having GPUOBJ and VM intertwined like this makes it *really* hard to continue porting to the new driver architecture, split it out in favour of requiring explit maps be the caller. It's more flexible and obvious this way anyway... Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
The partial mapping thing is stupid and pointless... Signed-off-by: -
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Ben Skeggs authored
These type of fake objects will not be supported for much longer. Signed-off-by: -
Ben Skeggs authored
A ton of duplication for the moment, will go away when they become subdevs. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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v2: - make sure not to execute display scripts unless resuming Signed-off-by: -
Ben Skeggs authored
Still missing the main bits we use to change performance levels, I'll get to it after all the hard yakka has been finished. Signed-off-by: -
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