- 12 Jan, 2011 40 commits
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Marcelo Tosatti authored
If a pagetable contains a writeable large spte, all of its sptes will be write protected, including non-leaf ones, leading to endless pagefaults. Do not write protect pages above PT_PAGE_TABLE_LEVEL, as the spte fault paths assume non-leaf sptes are writable. Tested-by:
Alex Williamson <alex.williamson@redhat.com> Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com>
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Avi Kivity authored
'error' is byte sized, so use a byte register constraint. Acked-by:
Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by:
Avi Kivity <avi@redhat.com> Signed-off-by:
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Avi Kivity authored
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Avi Kivity authored
When NX is enabled on the host but not on the guest, we use the entry/exit msr load facility, which is slow. Optimize it to use entry/exit efer load, which is ~1200 cycles faster. Signed-off-by:
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Avi Kivity authored
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Andre Przywara authored
In case of a nested page fault or an intercepted #PF newer SVM implementations provide a copy of the faulting instruction bytes in the VMCB. Use these bytes to feed the instruction emulator and avoid the costly guest instruction fetch in this case. Signed-off-by:
Andre Przywara <andre.przywara@amd.com> Signed-off-by:
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Andre Przywara authored
When the DecodeAssist feature is available, the linear address is provided in the VMCB on INVLPG intercepts. Use it directly to avoid any decoding and emulation. This is only useful for shadow paging, though. Signed-off-by:
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Andre Przywara authored
Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle debug register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by:
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Andre Przywara authored
Newer SVM implementations provide the GPR number in the VMCB, so that the emulation path is no longer necesarry to handle CR register access intercepts. Implement the handling in svm.c and use it when the info is provided. Signed-off-by:
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Andre Przywara authored
the recent APM Vol.2 and the recent AMD CPUID specification describe new CPUID features bits for SVM. Name them here for later usage. Signed-off-by:
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Andre Przywara authored
emulate_instruction had many callers, but only one used all parameters. One parameter was unused, another one is now hidden by a wrapper function (required for a future addition anyway), so most callers use now a shorter parameter list. Signed-off-by:
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Andre Przywara authored
move the complete_insn_gp() helper function out of the VMX part into the generic x86 part to make it usable by SVM. Signed-off-by:
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Andre Przywara authored
The handling of CR8 writes in KVM is currently somewhat cumbersome. This patch makes it look like the other CR register handlers and fixes a possible issue in VMX, where the RIP would be incremented despite an injected #GP. Signed-off-by:
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Avi Kivity authored
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Takuya Yoshikawa authored
In KVM_CREATE_IRQCHIP, kvm_io_bus_unregister_dev() is called without taking slots_lock in the error handling path. Signed-off-by:
Takuya Yoshikawa <yoshikawa.takuya@oss.ntt.co.jp> Signed-off-by:
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Lai Jiangshan authored
userspace may check this extension in runtime. Signed-off-by:
Lai Jiangshan <laijs@cn.fujitsu.com> Signed-off-by:
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Avi Kivity authored
Currently, we record '1' for count regardless of the real count. Fix. Signed-off-by: -
Avi Kivity authored
If KVM sees a read-only host page, it will map it as read-only to prevent breaking a COW. However, if the page was part of a large guest page, KVM incorrectly extends the write protection to the entire large page frame instead of limiting it to the normal host page. This results in the instantiation of a new shadow page with read-only access. If this happens for a MOVS instruction that moves memory between two normal pages, within a single large page frame, and mapped within the guest as a large page, and if, in addition, the source operand is not writeable in the host (perhaps due to KSM), then KVM will instantiate a read-only direct shadow page, instantiate an spte for the source operand, then instantiate a new read/write direct shadow page and instantiate an spte for the destination operand. Since these two sptes are in different shadow pages, MOVS will never see them at the same time and the guest will not make progress. Fix by mapping the direct shadow page read/write, and only marking the host page read-only. Signed-off-by: -
Avi Kivity authored
Make it available for all archs. Signed-off-by: -
Joerg Roedel authored
This patch implements the xsetbv intercept to the AMD part of KVM. This makes AVX usable in a save way for the guest on AVX capable AMD hardware. The patch is tested by using AVX in the guest and host in parallel and checking for data corruption. I also used the KVM xsave unit-tests and they all pass. Signed-off-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
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Takuya Yoshikawa authored
Large page information has two elements but one of them, write_count, alone is accessed by a helper function. This patch replaces this helper function with more generic one which returns newly named kvm_lpage_info structure and use it to access the other element rmap_pde. Signed-off-by:
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Anthony Liguori authored
In certain use-cases, we want to allocate guests fixed time slices where idle guest cycles leave the machine idling. There are many approaches to achieve this but the most direct is to simply avoid trapping the HLT instruction which lets the guest directly execute the instruction putting the processor to sleep. Introduce this as a module-level option for kvm-vmx.ko since if you do this for one guest, you probably want to do it for all. Signed-off-by:
Anthony Liguori <aliguori@us.ibm.com> Signed-off-by:
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Joerg Roedel authored
This patch adds the new flush-by-asid of upcoming AMD processors to the KVM-AMD module. Signed-off-by:
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Joerg Roedel authored
This patch replaces all calls to force_new_asid which are intended to flush the guest-tlb by the more appropriate function svm_flush_tlb. As a side-effect the force_new_asid function is removed. Signed-off-by:
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Joerg Roedel authored
This function is unused and there is svm_flush_tlb which does the same. So this function can be removed. Signed-off-by:
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Xiao Guangrong authored
Retry #PF for softmmu only when the current vcpu has the same cr3 as the time when #PF occurs Signed-off-by:
Xiao Guangrong <xiaoguangrong@cn.fujitsu.com> Signed-off-by:
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Xiao Guangrong authored
Retry #PF is the speculative path, so don't set the accessed bit Signed-off-by:
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Xiao Guangrong authored
It's the speculative path if 'no_apf = 1' and we will specially handle this speculative path in the later patch, so 'prefault' is better to fit the sense. Signed-off-by:
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Joerg Roedel authored
This patch implements the clean-bit for all LBR related state. This includes the debugctl, br_from, br_to, last_excp_from, and last_excp_to msrs. Signed-off-by:
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Joerg Roedel authored
This patch implements the clean-bit for the cr2 register in the vmcb. Signed-off-by:
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Joerg Roedel authored
This patch implements the clean-bit defined for the cs, ds, ss, an es segemnts and the current cpl saved in the vmcb. Signed-off-by:
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Joerg Roedel authored
This patch implements the clean-bit for the base and limit of the gdt and idt in the vmcb. Signed-off-by:
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Joerg Roedel authored
This patch implements the clean-bit for the dr6 and dr7 debug registers in the vmcb. Signed-off-by:
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Joerg Roedel authored
This patch implements the CRx clean-bit for the vmcb. This bit covers cr0, cr3, cr4, and efer. Signed-off-by:
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Joerg Roedel authored
This patch implements the clean-bit for all nested paging related state in the vmcb. Signed-off-by:
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Joerg Roedel authored
This patch implements the clean-bit for all interrupt related state in the vmcb. This corresponds to vmcb offset 0x60-0x67. Signed-off-by:
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Joerg Roedel authored
This patch implements the clean-bit for the asid in the vmcb. Signed-off-by:
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Joerg Roedel authored
This patch adds the clean bit for the physical addresses of the MSRPM and the IOPM. It does not need to be set in the code because the only place where these values are changed is the nested-svm vmrun and vmexit path. These functions already mark the complete VMCB as dirty. Signed-off-by:
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Joerg Roedel authored
This patch adds the clean-bit for intercepts-vectors, the TSC offset and the pause-filter count to the appropriate places. The IO and MSR permission bitmaps are not subject to this bit. Signed-off-by:
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Roedel, Joerg authored
This patch adds the infrastructure for the implementation of the individual clean-bits. Signed-off-by:
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