- 11 Apr, 2013 4 commits
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Kumar Gala authored
The localbus node should be in at 0xfffe05000 not 0xffe05000. Also fixed the names of the localbus and pci nodes to reflect the addresses they are actually at. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com> Signed-off-by:
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Roy ZANG authored
Some 85xx board, for example, P1020RDB-PC has on board silicon image PCIe to SATA controller and when booting up, the filesystem will auto mount to the SATA disk. So enable silicon image 3132 pcie to sata controller by default Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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Vakul Garg authored
The crypto node now contains a new property 'fsl,sec-era'. This is required so that applications can retrieve era info without having to be able to read SEC's register space. Signed-off-by:
Vakul Garg <vakul@freescale.com> Signed-off-by:
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Vakul Garg authored
Removing qoriq-sec4.1-0.dtsi as it is not used by any soc anymore. Signed-off-by:
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- 10 Apr, 2013 7 commits
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Shaveta Leekha authored
Signed-off-by:
Shaveta Leekha <shaveta@freescale.com> Signed-off-by:
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Shaveta Leekha authored
- Add support for B4 board in board file b4_qds.c, It is common for B4860, B4420 and B4220QDS as they share same QDS board - Add B4QDS support in Kconfig and Makefile B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor, with following major features: - Four dual-threaded e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz - Two DDR3/3L controllers for high-speed memory interface each runs at up to 1866.67 MHz - CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3 and RMAN - Large internal cache memory with snooping and stashing capabilities - Sixteen 10-GHz SerDes lanes that serve: - Two SRIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes - Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less antenna connection - Two 10-Gbit Ethernet controllers (10GEC) - Six 1G/2.5-Gbit Ethernet controllers for network communications - PCI Express controller - Debug (Aurora) - Various system peripherals B4420 and B4220 have some differences in comparison to B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420: B4420 has: - Fewer e6500 cores: 1 cluster with 2 e6500 cores - Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster - Single DDRC @ 1.6GHz - 2 X 4 lane serdes - 3 SGMII interfaces - no sRIO - no 10G Key differences between B4860 and B4220: B4220 has: - Fewer e6500 cores: 1 cluster with 1 e6500 core - Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster - Single DDRC @ 1.33GHz - 2 X 2 lane serdes - 2 SGMII interfaces - no sRIO - no 10G Signed-off-by: -
Shaveta Leekha authored
B4860QDS and B4420QDS share same QDS board * common board features have been added in b4qds.dts * various board differences are in respective files of B4860 and B4420 Signed-off-by:
Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com> Signed-off-by:
Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by:
Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by:
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Shaveta Leekha authored
B4860 and B4420 are similar that share some commonalities * common features have been added in b4si-pre.dtsi and b4si-post.dtsi * differences are added in respective silicon files of B4860 and B4420 There are several things missing from the device trees of B4860 and B4420: * DPAA related nodes (Qman, Bman, Fman, Rman) * DSP related nodes/information * serdes, sfp(security fuse processor), thermal, gpio, maple, cpri, quad timers nodes Signed-off-by:
Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by:
Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by:
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Rojhalat Ibrahim authored
Up to now the PCIe link status on Freescale PCIe controllers was only checked once at boot time. So hotplug did not work. With this patch the link status is checked on every config read. PCIe devices not present at boot time are found after doing 'echo 1 >/sys/bus/pci/rescan'. Signed-off-by:
Rojhalat Ibrahim <imr@rtschenk.de> Signed-off-by:
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Kumar Gala authored
Move to keeping the SoC registers that control and config the PCI controllers on FSL SoCs in the pci_controller struct. This allows us to not need to ioremap() the registers in multiple different places that use them. Signed-off-by: -
Paul Bolle authored
The last users of Kconfig symbol MPC10X_OPENPIC were removed in v2.6.27. Its Kconfig entry can be removed now. Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Signed-off-by:
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- 09 Apr, 2013 1 commit
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Kumar Gala authored
* Fix cpu unit address to match reg * Update compatible for rcpm & clockgen to be 2.0 instead of 2 Signed-off-by:
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- 03 Apr, 2013 5 commits
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Chen-Hui Zhao authored
mpic_reset_core() need a logical cpu number instead of physical. Signed-off-by:
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Sebastian Andrzej Siewior authored
lockdep thinks that it might deadlock because it grabs a lock of the same class while calling the generic_irq_handler(). This annotation will inform lockdep that it will not. Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
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Shaveta Leekha authored
Signed-off-by:
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Roy Zang authored
The size might be 64 bit, so use ilog2() instead of __ilog2() or __ilog2_u64(). ilog2() can select 32bit or 64bit function automatically. Signed-off-by:
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Ben Collins authored
Somehow the driver snuck in with these still in it. Signed-off-by:
Ben Collins <ben.c@servergy.com> Signed-off-by:
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- 18 Mar, 2013 4 commits
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Kumar Gala authored
As the T4240 is based on corenet chassis v2.0 spec we update the global utilities (GUTS) device config compatiable to reflect this. Signed-off-by: -
Stephen George authored
Identifies the epu as compatible with Chassis v1 Debug IP. Signed-off-by:
Stephen George <Stephen.George@freescale.com> Signed-off-by:
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Stephen George authored
Signed-off-by:
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Prabhakar Kushwaha authored
Add CONFIG(s) required for NAND and NOR flash controller usage. It defines MTD, Jffs2 and UBIFS file system required for controllers. It also enables IFC controller Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by:
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- 15 Mar, 2013 4 commits
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Kumar Gala authored
Commit 193ab2a6 changed the USB gadget Kconfig symbol from USB_GADGET_FSL_QE to USB_FSL_QE, but did not update the associated symbol name in qe_lib to match. Signed-off-by:
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Jia Hongtao authored
mpc85xx_pci_err_probe(struct platform_device *op) need platform_device declaration for definition. Otherwise, it will cause compile error if any files including fsl_pci.h without declaration of platform_device. Signed-off-by:
Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by:
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Paul Bolle authored
The last user of Kconfig symbol 8260_PCI9 got removed in release v3.2. Remove this symbol too. Signed-off-by:
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Roy Zang authored
E1000 NIC is a common used Ethernet card. Enable it as default for mpc85xx platform. other change is due to make savedefconfig Reported-by:
Fu Jiwei <b36666@freescale.com> Signed-off-by:
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- 13 Mar, 2013 1 commit
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Stuart Yoder authored
Signed-off-by:
Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by:
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- 12 Mar, 2013 9 commits
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Scott Wood authored
This is a commonly used ethernet card, especially with mainline kernels which lack datapath support. Signed-off-by:
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Tang Yuantian authored
Config FSL_SOC does not depend on PPC_CLOCK anymore since the following commit got merged: 93abe8e4 (clk: add non CONFIG_HAVE_CLK routines) Config CPM does not use PPC_CLOCK either currently. So remove them. PPC_CLOCK also keeps Freescale PowerPC archtecture from supporting COMMON_CLK. Signed-off-by:
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Jiucheng Xu authored
Due to the partition of JFFS2 overlaps with QE ucode firmware, So JFFS2 will break QE ucode. Shrink JFFS2's partition to reserve the space of QE ucode firmware. Signed-off-by:
Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by:
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Ramneek Mehresh authored
Add first usb controller node for qonverge qoriq platforms like B4860, etc Signed-off-by:
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Kumar Gala authored
* Add support for up to 24 cores on T4240 (includes threads) * Enable AltiVec support (on T4240) * Add T4240QDS board into build * Other changes are due to general kernel update of defconfig Signed-off-by: -
Kumar Gala authored
Some minor changes to the common corenet_ds.c code are needed to support the T4240QDS: * Add support for "fsl,qoriq-pcie-v3.0" controller * Bump max # of IRQs to 512 (T4240 supports more interrupts than previous SoCs). Signed-off-by: -
Kumar Gala authored
Signed-off-by:
Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by:
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Kumar Gala authored
Enable a baseline T4240 SoC to boot. There are several things missing from the device trees for T4240: * Proper PAMU topology information * DPAA related nodes (Qman, Bman, Fman, Rman, DCE) * Prefetch Manager * Thermal monitor unit * Interlaken Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by:
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Kumar Gala authored
The e6500 core adds support for AltiVec on a Book-E class processor. Connect up all the various exception handling code and build config mechanisms to allow user spaces apps to utilize AltiVec. Signed-off-by:
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- 05 Mar, 2013 5 commits
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Kumar Gala authored
The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of the Power Book-E Architecture. However there are some minor differences between it and other Book-E implementations. Add support to parse SPRN_TLB1PS for the variable page sizes supported. In the future this should be expanded for more page sizes supported on e6500 as well as other MMU features. This patch is based on code from Scott Wood. Signed-off-by: -
Roy ZANG authored
The T4240 utilizes a new PCIe controller block that has some minor programming model differences from previous versions. The major one that impacts initialization is how we determine the link state. On the 3.x controllers we have a memory mapped SoC register instead of a PCI config register that reports the link state. Signed-off-by:
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Vakul Garg authored
Add device tree for SEC (crypto engine) version 5.0 used on T4240. Signed-off-by:
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Stuart Yoder authored
Signed-off-by:
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Stuart Yoder authored
-also define a binding for fsl,eref-* properties Signed-off-by:
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