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  1. 29 Dec, 2015 11 commits
  3. 23 Dec, 2015 1 commit
  5. 21 Dec, 2015 4 commits
  7. 20 Dec, 2015 1 commit
  9. 19 Dec, 2015 2 commits
  11. 18 Dec, 2015 5 commits
  13. 16 Dec, 2015 11 commits
    • Marc Zyngier's avatar
      irqchip/gic: Make interrupt ID 1020 invalid · 327ebe1f
      Marc Zyngier authored 
      The GIC has no such thing as interrupt 1020: the last valid ID is
1019, and the range 1020-1023 is reserved - 1023 indicating that
no interrupt is pending. So let's make sure we don't try to handle
this ID.

This bug has been in since the initial GIC code was introduced in
8ad68bbf ("[ARM] Add support for ARM RealView board").
Reported-by: default avatarEric Auger <eric.auger@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      327ebe1f
    • Marc Zyngier's avatar
      irqchip/gic-v2m: Fix of_node refcount on error · 86d14c72
      Marc Zyngier authored 
      On the error path, the v2m drivers drops the refcount on the parent
node instead of doing it on the node that generated the error.
Humph...
Reported-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      86d14c72
    • Linus Walleij's avatar
      irqchip/gic: Assign irqchip dynamically · 58b89649
      Linus Walleij authored 
      Instead of having the irqchip being a static struct, make it part
of the per-instance data so we can assign it a dynamic name. This
has the usable side effect of displaying the GIC with an instance
number as GIC0, GIC1 ... GICn in /proc/interrupts, which is helpful
when debugging cascaded GICs, such as on the ARM PB11MPCore.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      58b89649
    • Linus Walleij's avatar
      irqchip/gic: Support RealView variant setup · 8673c1d7
      Linus Walleij authored 
      The ARM RealView PB11MPCore reference design has some special
bits in a system controller register to set up the GIC in one
of three modes: legacy, new with DCC, new without DCC. The
register is also used to enable FIQ.

Since the platform will not boot unless this register is set
up to "new with DCC" mode, we need a special quirk to be
compiled-in for the RealView platforms.

If we find the right compatible string on the GIC TestChip,
we enable this quirk by looking up the system controller and
enabling the special bits.

We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old
boardfile code has the same fix hardcoded, and this is only
needed for the attempts to modernize the RealView code using
device tree.

After fixing this, the PB11MPCore boots with device tree
only.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      8673c1d7
    • Linus Walleij's avatar
      irqchip/gic: Fix ARM11MPCore GIC bindings · 126aebd0
      Linus Walleij authored 
      The GIC bindings for the ARM11MPCore need to differentiate between
the GIC on the Test Chip and the one on the evaluation baseboard.
Split the binding in two and define new compatible-strings.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      126aebd0
    • Marc Zyngier's avatar
      platform-msi: Allow creation of a MSI-based stacked irq domain · 552c494a
      Marc Zyngier authored 
      We almost have all the needed bits requiredable to create a irq domain
on top of a MSI domain.

For this, we enable a few things:
- the virq is stored in the msi_desc
- device, msi_alloc_info and domain-specific data
  are stored in the platform_priv_data structure
- we introduce a new API for platform-msi:

  /* Create a MSI-based domain */
  struct irq_domain *
  platform_msi_create_device_domain(struct device *dev,
                                    unsigned int nvec,
                                    irq_write_msi_msg_t write_msi_msg,
                                    const struct irq_domain_ops *ops,
                                    void *host_data);

  /* Allocate MSIs in an MSI domain */
  int platform_msi_domain_alloc(struct irq_domain *domain,
				unsigned int virq,
				unsigned int nr_irqs);

  /* Free MSIs from an MSI domain */
  void platform_msi_domain_free(struct irq_domain *domain,
				unsigned int virq,
				unsigned int nvec);

  /* Obtain the host data passed to platform_msi_create_device_domain */
  void *platform_msi_get_host_data(struct irq_domain *domain);

platform_msi_create_device_domain() is a hybrid of irqdomain creation
and interrupt allocation, creating a domain backed by the MSIs associated
to a device. IRQs can then be allocated in that domain using
platform_msi_domain_alloc().

This now allows a wired irq to MSI bridge to be created.
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      552c494a
    • Marc Zyngier's avatar
      genirq/msi: Add msi_domain_populate_irqs · 2145ac93
      Marc Zyngier authored 
      To be able to allocate interrupts from the MSI layer down,
add a new msi_domain_populate_irqs entry point.
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      2145ac93
    • Marc Zyngier's avatar
      genirq/msi: Make the .prepare callback reusable · b2eba39b
      Marc Zyngier authored 
      The .prepare callbacks are so far only called from msi_domain_alloc_irqs.
In order to reuse that code, split that code and create a
msi_domain_prepare_irqs function that the existing code can call into.
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      b2eba39b
    • Marc Zyngier's avatar
      irqdomain: Make irq_domain_alloc_irqs_recursive available · c466595c
      Marc Zyngier authored 
      We are soon going to need the MSI layer to call into the domain
allocators. Instead of open coding this, make the standard
irq_domain_alloc_irqs_recursive function available to the MSI
layer.
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      c466595c
    • Marc Zyngier's avatar
      platform-msi: Factor out allocation/free of private data · 72f57f2f
      Marc Zyngier authored 
      As we're going to have multiple paths to allocate/free the
platform-msi private data, factor this out into separate
utility functions.
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      72f57f2f
    • Marc Zyngier's avatar
      platform-msi: Allow MSIs to be allocated in chunks · ab6484ee
      Marc Zyngier authored 
      MSIs for a given device are normally all allocated in one go.
Make sure the internal code can allocate them one at a time
if required.
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      ab6484ee
  15. 14 Dec, 2015 2 commits
    • Thomas Gleixner's avatar
      genirq: Free irq_desc with rcu · 425a5072
      Thomas Gleixner authored 
      The new VMD device driver needs to iterate over a list of
"demultiplexing" interrupts. Protecting that list with a lock is not
possible because the list is also required in code pathes which hold
irq descriptor lock. Therefor the demultiplexing interrupt handler
would create a lock inversion scenario if it calls a demux handler
with the list protection lock held.

A solution for this is to free the irq descriptor via RCU, so the
list can be walked with rcu read lock held.
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Keith Busch <keith.busch@intel.com>
      425a5072
    • Linus Torvalds's avatar
      Linux 4.4-rc5 · 9f9499ae
      Linus Torvalds authored
      9f9499ae
  17. 13 Dec, 2015 3 commits
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