- 25 Apr, 2017 3 commits
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Steven J. Hill authored
Enable the Octeon MMC driver in the defconfig. Signed-off-by:
Steven J. Hill <Steven.Hill@cavium.com> Acked-by:
Ralf Baechle <ralf@linux-mips.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Wei Yongjun authored
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
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Wei Yongjun authored
Use the module_pci_driver() macro to make the code simpler by eliminating module_init and module_exit calls. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
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- 24 Apr, 2017 37 commits
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Steven J. Hill authored
Add platform driver for Octeon SOCs. Signed-off-by:
David Daney <david.daney@cavium.com> Signed-off-by:
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Steven J. Hill authored
Use the mmc_card_is_blockaddr() function to properly detect if the card uses byte or block addressing. Signed-off-by:
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Ulf Hansson authored
Some hosts controllers, like Cavium, needs to know whether the card operates in byte- or block-address mode. Therefore export a new API, mmc_card_is_blockaddr(), which provides this information. Signed-off-by:
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jiajie.hao@mediatek.com authored
The host may issue an I/O abort by writing to the CCCR at any time during I/O read operation via CMD52. And host may need suspend transcation during write busy stage in SDIO suspend/resume scenario. >From other side, a card may accept CMD52 during data transfer phase. Previous implement would block issuing above command in busy stage. It cause function driver can't implement as proper way and has no opportunity to do some coverage in error case via I/O abort etc. We need bypass some necessary operation during busy check stage. Signed-off-by:
Jiajie Hao <jiajie.hao@mediatek.com> Signed-off-by:
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Haibo Chen authored
USDHC tuning circuit should be reset before every time card enumeration or re-enumeration. SD3.0 card need tuning. For SDR104 card, when system suspend in standby mode, and then resume back, the IO timing is still SDR104(tuned) which may result in card re-enumeration fail in low card speed(400khz) for some cards. And we did meet the issue that in certain probability, SDR104 card meet mmc command CRC/Timeout error when send CMD2 during mmc bus resume. This patch reset the tuning circuit when the ios timing is MMC_TIMING_LEGACY/MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS, which means both mmc_power_up() and mmc_power_off() will reset the tuning circuit. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Dong Aisheng <aisheng.dong@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
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Colin Ian King authored
trivial fix to spelling mistake in dev_warn message Signed-off-by:
Colin Ian King <colin.king@canonical.com> Acked-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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yangbo lu authored
It's observed that eSDHC needed delay between tuning cycles for HS200 successful tuning. This patch is to set 1ms delay for that. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Acked-by:
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Adrian Hunter authored
The delay between tuning commands for SD cards is not part of the specification. A driver that needs it probably needs it for eMMC too, whereas most drivers would probably like to set it to 0. Make it a host member (host->tuning_delay) that defaults to the existing behaviour. Drivers can set it to zero to eliminate the delay, or set it to a positive value to always have a delay. Signed-off-by:
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yangbo lu authored
eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by:
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yangbo lu authored
eSDHC supports signal voltage switch from 3.3v to 1.8v by eSDHC_PROCTL[VOLT_SEL] bit. This bit changes the value of output signal SDHC_VS, and there must be a control circuit out of eSDHC to change the signal voltage according to SDHC_VS output signal. Signed-off-by:
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yangbo lu authored
eSDHC could select peripheral clock or platform clock as clock source by the PCS bit of eSDHC Control Register, and this bit couldn't be reset by software reset for all. In default, the platform clock is used. But we have to use peripheral clock since it has a higher frequency to support eMMC HS200 mode and SD UHS-I mode. This patch is to add peripheral clock support and use it instead of platform clock if it's declared in eSDHC dts node. Signed-off-by:
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Adrian Hunter authored
The DSM used by some Intel controllers can return a 3 byte package. Allow for that by using memcpy to copy the bytes. Signed-off-by:
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Dan Carpenter authored
"dat" is a u64 and "shift" starts as 54 so this is a shift wrapping bug. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Jan Glauber authored
Add a pointer check to prevent this smatch warning: drivers/mmc/host/cavium.c:803 cvm_mmc_request() error: we previously assumed 'cmd->data' could be null (see line 782) This is a theoretical fix because MMC_CMD_ADTC seems to imply that cmd->data is not null. Nevertheless checking cmd->data before using it improves readability. Signed-off-by:
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Jan Glauber authored
Remove redundant mmc->card check reported by smatch: drivers/mmc/host/cavium.c:694 cvm_mmc_dma_request() warn: variable dereferenced before check 'mmc->card' (see line 675) Signed-off-by:
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Heiner Kallweit authored
So far a bounce buffer is used to serialize the scatterlist(s). This overhead can be avoided by switching to descriptor chain mode. As result the performance is drastically improved. On a Odroid-C2 with a 128 GB eMMC module raw reads reach 140 MB/s. Prerequisite for descriptor chain mode is that all scatterlist buffers are 8 byte aligned for 64-bit DMA. That's not always the case, at least the brcmfmac SDIO WiFi driver is known to cause problems. Therefore, for each request, check upfront whether all scatterlist buffers are 8 byte aligned and fall back to bounce buffer mode if that's not the case. Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
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Heiner Kallweit authored
This patch adds basic tuning which changes the rx clock phase only until a working setting is found. On a Odroid C2 with 128GB eMMC card and 200 MHz MMC clock only 180° rx clock phase make the system boot w/o CRC errors. With other MMC devices / clock speeds this might be different, therefore don't change the driver config in general. When retuning skip the currently active parameter set. This avoids the current problematic config to be chosen again if it causes CRC errors just occasionally. Signed-off-by:
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Heiner Kallweit authored
Introduce struct meson_tuning_params for storing the clock phase configurations. There's no functional change because tx and rx clock phase were implicitely set to CLK_PHASE_0 before. Signed-off-by:
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Winkler, Tomas authored
Annotate big endian values correctly and make sparse happy. In mmc_app_send_scr remove scr function parameter as it was updating card->raw_scr anyway. Signed-off-by:
Tomas Winkler <tomas.winkler@intel.com> Signed-off-by:
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Piotr Sroka authored
Add calling sdhci_get_of_property function to parse sdhci properties. Signed-off-by:
Piotr Sroka <piotrs@cadence.com> Acked-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Dan Carpenter authored
devm_pinctrl_get() returns error pointers, it never returns NULL. Fixes: 455e5cd6 ("mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335x") Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Hu Ziji authored
Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host Controller drivers. Signed-off-by:
Hu Ziji <huziji@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Hu Ziji authored
Some SoCs have PHY PAD outside Xenon IP. PHY PAD voltage should match signalling voltage in use. Add generic SoC PHY PAD voltage control interface. Implement Aramda-3700 SoC PHY PAD voltage control. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
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Hu Ziji authored
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY. Multiple types of PHYs are supported. Add support to multiple types of PHYs init and configuration. Add register definitions of PHYs. Xenon PHY cannot fit in kernel common PHY framework. Xenon SDHC PHY register is a part of Xenon SDHC register set. Besides, MMC initialization has to call several PHY functions to complete timing setting. Those PHY setting functions have to access SDHC registers and know current MMC setting, such as bus width, clock frequency and speed mode. As a result, implement Xenon PHY in MMC host directory. Signed-off-by:
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Hu Ziji authored
Add Xenon eMMC/SD/SDIO host controller core functionality. Add Xenon specific initialization process. Add Xenon specific mmc_host_ops APIs. Add Xenon specific register definitions. Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig. Marvell Xenon SDHC conforms to SD Physical Layer Specification Version 3.01 and is designed according to the guidelines provided in the SD Host Controller Standard Specification Version 3.00. Signed-off-by:
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Hu Ziji authored
Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Hu Ziji authored
Export sdhci_enable_sdio_irq() from sdhci.c. Thus vendor SDHC driver can implement its specific SDIO irq control. Signed-off-by:
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Hu Ziji authored
Export sdhci_start_signal_voltage_switch() from sdhci.c. Thus vendor sdhci driver can implement its own signal voltage switch routine. Signed-off-by:
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Hu Ziji authored
Export sdhci_set_ios() in sdhci.c. Thus vendor sdhci driver can implement its own set_ios() routine. Signed-off-by:
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Gregory CLEMENT authored
First version of the binding didn't have the eMMC clock. This patch allows to not registering the eMMC clock if it is not present in the device tree. Then the device tree can be backwards compatible. Suggested-by:
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Konstantin Porotchkin authored
Add fixed clock of 400MHz to system controller driver. This clock is used as SD/eMMC clock source. Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com> Reviewed-by:
Omri Itach <omrii@marvell.com> Reviewed-by:
Hanna Hawa <hannah@marvell.com> [fixed up conflicts, added error handling --rmk] Signed-off-by:
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Jan Glauber authored
Signed-off-by:
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Jan Glauber authored
Add support for switching to DDR mode for eMMC devices. Signed-off-by:
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Jan Glauber authored
Add Support for the scatter-gather DMA available in the ThunderX MMC units. Up to 16 DMA requests can be processed together. Signed-off-by:
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Jan Glauber authored
Add a platform driver for ThunderX ARM SOCs. Signed-off-by:
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Jan Glauber authored
This core driver will be used by a MIPS platform driver or by an ARM64 PCI driver. The core driver implements the mmc_host_ops and slot probe & remove functions. Callbacks are provided to allow platform specific interrupt enable and bus locking. The host controller supports: - up to 4 slots that can contain sd-cards or eMMC chips - 1, 4 and 8 bit bus width - SDR and DDR - transfers up to 52 Mhz (might be less when multiple slots are used) - DMA read/write - multi-block read/write (but not stream mode) Voltage is limited to 3.3v and shared for all slots (vmmc and vmmcq). A global lock for all MMC devices is required because the host controller is shared. Signed-off-by:
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Jan Glauber authored
Add description of Cavium Octeon and ThunderX SOC device tree bindings. CC: Ulf Hansson <ulf.hansson@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: devicetree@vger.kernel.org Signed-off-by:
Rob Herring <robh+dt@kernel.org> Signed-off-by:
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