Using __ppc_get_timebase will translate to mfspr instruction
The mfspr instruction will block FXU1 until complete but the other
Pipelines are available for execution of instructions from other
SMT threads on the same core.

The latency time to read the timebase SPR is ~10 cycles.

So any impact on other threads is limited other FXU1 only instructions
(basically other mfspr/mtspr ops).

Suggested by Steven J. Munroe, Linux on Power Toolchain Architect,
Linux Technology Center
IBM Corporation