Skip to content

M
MariaDB
Commit b62d2ac0 authored by unknown's avatar unknown
Browse files
Options

Use native format in interpreter - 

(old code mixed the 3 alternatives: native, [lo, hi], [hi, lo])

This fixes problem with auto increment on different byte order

(This also make adding of signed ints really simple...)


ndb/src/kernel/blocks/dbtup/DbtupExecQuery.cpp:
  Use native format in interpreter
  (old code mixed the 3 alternatives: native, [lo, hi], [hi, lo])
ndb/src/ndbapi/Ndb.cpp:
  Use native format in interpreter
  (old code mixed the 3 alternatives: native, [lo, hi], [hi, lo])
ndb/src/ndbapi/NdbOperationInt.cpp:
  Use native format in interpreter
  (old code mixed the 3 alternatives: native, [lo, hi], [hi, lo])
parent 23b76504
Show whitespace changes
Inline Side-by-side
Showing with 50 additions and 94 deletions
ndb/src/kernel/blocks/dbtup/DbtupExecQuery.cpp
View file @ b62d2ac0
...@@ -1505,6 +1505,8 @@ int Dbtup::interpreterNextLab(Signal* signal, ...@@ -1505,6 +1505,8 @@ int Dbtup::interpreterNextLab(Signal* signal,
// the register to indicate a NULL value. // the register to indicate a NULL value.
/* ------------------------------------------------------------- */ /* ------------------------------------------------------------- */
TregMemBuffer[theRegister] = 0; TregMemBuffer[theRegister] = 0;
TregMemBuffer[theRegister + 1] = 0;
TregMemBuffer[theRegister + 2] = 0;
} else if (TnoDataRW == (Uint32)-1) { } else if (TnoDataRW == (Uint32)-1) {
jam(); jam();
tupkeyErrorLab(signal); tupkeyErrorLab(signal);
...@@ -1593,23 +1595,22 @@ int Dbtup::interpreterNextLab(Signal* signal, ...@@ -1593,23 +1595,22 @@ int Dbtup::interpreterNextLab(Signal* signal,
case Interpreter::LOAD_CONST16: case Interpreter::LOAD_CONST16:
jam(); jam();
TregMemBuffer[theRegister] = 0x50; /* 32 BIT UNSIGNED CONSTANT */ TregMemBuffer[theRegister] = 0x50; /* 32 BIT UNSIGNED CONSTANT */
TregMemBuffer[theRegister + 1] = theInstruction >> 16; * (Int64*)(TregMemBuffer+theRegister+1) = theInstruction >> 16;
TregMemBuffer[theRegister + 2] = 0;
break; break;
case Interpreter::LOAD_CONST32: case Interpreter::LOAD_CONST32:
jam(); jam();
TregMemBuffer[theRegister] = 0x50; /* 32 BIT UNSIGNED CONSTANT */ TregMemBuffer[theRegister] = 0x50; /* 32 BIT UNSIGNED CONSTANT */
TregMemBuffer[theRegister + 1] = TcurrentProgram[TprogramCounter]; * (Int64*)(TregMemBuffer+theRegister+1) = *
TregMemBuffer[theRegister + 2] = 0; (TcurrentProgram+TprogramCounter);
TprogramCounter++; TprogramCounter++;
break; break;
case Interpreter::LOAD_CONST64: case Interpreter::LOAD_CONST64:
jam(); jam();
TregMemBuffer[theRegister] = 0x60; /* 64 BIT UNSIGNED CONSTANT */ TregMemBuffer[theRegister] = 0x60; /* 64 BIT UNSIGNED CONSTANT */
TregMemBuffer[theRegister + 1] = TcurrentProgram[TprogramCounter + 0]; * (Int64*)(TregMemBuffer+theRegister+1) = * (Int64*)
TregMemBuffer[theRegister + 2] = TcurrentProgram[TprogramCounter + 1]; (TcurrentProgram+TprogramCounter);
TprogramCounter += 2; TprogramCounter += 2;
break; break;
...@@ -1620,27 +1621,16 @@ int Dbtup::interpreterNextLab(Signal* signal, ...@@ -1620,27 +1621,16 @@ int Dbtup::interpreterNextLab(Signal* signal,
Uint32 TdestRegister = Interpreter::getReg3(theInstruction) << 2; Uint32 TdestRegister = Interpreter::getReg3(theInstruction) << 2;
Uint32 TrightType = TregMemBuffer[TrightRegister]; Uint32 TrightType = TregMemBuffer[TrightRegister];
Uint32 Tright0 = TregMemBuffer[TrightRegister + 1]; Int64 Tright0 = * (Int64*)(TregMemBuffer + TrightRegister + 1);
Uint32 Tright1 = TregMemBuffer[TrightRegister + 2];
Uint32 TleftType = TregMemBuffer[theRegister]; Uint32 TleftType = TregMemBuffer[theRegister];
Uint32 Tleft0 = TregMemBuffer[theRegister + 1]; Int64 Tleft0 = * (Int64*)(TregMemBuffer + theRegister + 1);
Uint32 Tleft1 = TregMemBuffer[theRegister + 2];
Uint32 Tany64bit = (((TleftType | TrightType) & 0x60) == 0x60);
if ((TleftType | TrightType) != 0) { if ((TleftType | TrightType) != 0) {
Uint32 Tdest0 = Tleft0 + Tright0; Uint64 Tdest0 = Tleft0 + Tright0;
Uint32 Tdest1 = 0; * (Int64*)(TregMemBuffer+TdestRegister+1) = Tdest0;
TregMemBuffer[TdestRegister + 1] = Tdest0;
TregMemBuffer[TdestRegister] = 0x50;
if (Tany64bit) {
TregMemBuffer[TdestRegister] = 0x60; TregMemBuffer[TdestRegister] = 0x60;
Tdest1 = Tleft1 + Tright1;
if (Tdest0 < Tleft0) {
Tdest1++;
}
}//if
TregMemBuffer[TdestRegister + 2] = Tdest1;
} else { } else {
return TUPKEY_abort(signal, 20); return TUPKEY_abort(signal, 20);
} }
...@@ -1654,30 +1644,18 @@ int Dbtup::interpreterNextLab(Signal* signal, ...@@ -1654,30 +1644,18 @@ int Dbtup::interpreterNextLab(Signal* signal,
Uint32 TdestRegister = Interpreter::getReg3(theInstruction) << 2; Uint32 TdestRegister = Interpreter::getReg3(theInstruction) << 2;
Uint32 TrightType = TregMemBuffer[TrightRegister]; Uint32 TrightType = TregMemBuffer[TrightRegister];
Uint32 Tright0 = TregMemBuffer[TrightRegister + 1]; Int64 Tright0 = * (Int64*)(TregMemBuffer + TrightRegister + 1);
Uint32 Tright1 = TregMemBuffer[TrightRegister + 2];
Uint32 TleftType = TregMemBuffer[theRegister]; Uint32 TleftType = TregMemBuffer[theRegister];
Uint32 Tleft0 = TregMemBuffer[theRegister + 1]; Int64 Tleft0 = * (Int64*)(TregMemBuffer + theRegister + 1);
Uint32 Tleft1 = TregMemBuffer[theRegister + 2];
Uint32 Tany64bit = (((TleftType | TrightType) & 0x60) == 0x60);
if ((TleftType | TrightType) != 0) { if ((TleftType | TrightType) != 0) {
Uint32 Tdest0 = Tleft0 - Tright0; Int64 Tdest0 = Tleft0 - Tright0;
Uint32 Tdest1 = 0; * (Int64*)(TregMemBuffer+TdestRegister+1) = Tdest0;
TregMemBuffer[TdestRegister + 1] = Tdest0;
TregMemBuffer[TdestRegister] = 0x50;
if (Tany64bit) {
TregMemBuffer[TdestRegister] = 0x60; TregMemBuffer[TdestRegister] = 0x60;
Tdest1 = Tleft1 - Tright1;
if (Tdest0 > Tleft0) {
Tdest1--;
}//if
}//if
TregMemBuffer[TdestRegister + 2] = Tdest1;
} else { } else {
return TUPKEY_abort(signal, 21); return TUPKEY_abort(signal, 20);
}//if }
break; break;
} }
...@@ -1754,17 +1732,16 @@ int Dbtup::interpreterNextLab(Signal* signal, ...@@ -1754,17 +1732,16 @@ int Dbtup::interpreterNextLab(Signal* signal,
{ {
Uint32 TrightRegister = Interpreter::getReg2(theInstruction) << 2; Uint32 TrightRegister = Interpreter::getReg2(theInstruction) << 2;
Uint32 TrightType = TregMemBuffer[TrightRegister];
Int64 Tright0 = * (Int64*)(TregMemBuffer + TrightRegister + 1);
Uint32 TleftType = TregMemBuffer[theRegister]; Uint32 TleftType = TregMemBuffer[theRegister];
Uint32 Tleft0 = TregMemBuffer[theRegister + 1]; Int64 Tleft0 = * (Int64*)(TregMemBuffer + theRegister + 1);
Uint32 Tleft1 = TregMemBuffer[theRegister + 2];
Uint32 TrightType = TregMemBuffer[TrightRegister];
Uint32 Tright0 = TregMemBuffer[TrightRegister + 1];
Uint32 Tright1 = TregMemBuffer[TrightRegister + 2];
if ((TrightType | TleftType) != 0) { if ((TrightType | TleftType) != 0) {
jam(); jam();
if ((Tleft0 < Tright0) || ((Tleft0 == Tright0) && if (Tleft0 < Tright0) {
(Tleft1 < Tright1))) {
TprogramCounter = brancher(theInstruction, TprogramCounter); TprogramCounter = brancher(theInstruction, TprogramCounter);
}//if }//if
} else { } else {
...@@ -1777,17 +1754,16 @@ int Dbtup::interpreterNextLab(Signal* signal, ...@@ -1777,17 +1754,16 @@ int Dbtup::interpreterNextLab(Signal* signal,
{ {
Uint32 TrightRegister = Interpreter::getReg2(theInstruction) << 2; Uint32 TrightRegister = Interpreter::getReg2(theInstruction) << 2;
Uint32 TrightType = TregMemBuffer[TrightRegister];
Int64 Tright0 = * (Int64*)(TregMemBuffer + TrightRegister + 1);
Uint32 TleftType = TregMemBuffer[theRegister]; Uint32 TleftType = TregMemBuffer[theRegister];
Uint32 Tleft0 = TregMemBuffer[theRegister + 1]; Int64 Tleft0 = * (Int64*)(TregMemBuffer + theRegister + 1);
Uint32 Tleft1 = TregMemBuffer[theRegister + 2];
Uint32 TrightType = TregMemBuffer[TrightRegister];
Uint32 Tright0 = TregMemBuffer[TrightRegister + 1];
Uint32 Tright1 = TregMemBuffer[TrightRegister + 2];
if ((TrightType | TleftType) != 0) { if ((TrightType | TleftType) != 0) {
jam(); jam();
if ((Tleft0 < Tright0) || ((Tleft0 == Tright0) && if (Tleft0 <= Tright0) {
(Tleft1 <= Tright1))) {
TprogramCounter = brancher(theInstruction, TprogramCounter); TprogramCounter = brancher(theInstruction, TprogramCounter);
}//if }//if
} else { } else {
...@@ -1800,17 +1776,16 @@ int Dbtup::interpreterNextLab(Signal* signal, ...@@ -1800,17 +1776,16 @@ int Dbtup::interpreterNextLab(Signal* signal,
{ {
Uint32 TrightRegister = Interpreter::getReg2(theInstruction) << 2; Uint32 TrightRegister = Interpreter::getReg2(theInstruction) << 2;
Uint32 TrightType = TregMemBuffer[TrightRegister];
Int64 Tright0 = * (Int64*)(TregMemBuffer + TrightRegister + 1);
Uint32 TleftType = TregMemBuffer[theRegister]; Uint32 TleftType = TregMemBuffer[theRegister];
Uint32 Tleft0 = TregMemBuffer[theRegister + 1]; Int64 Tleft0 = * (Int64*)(TregMemBuffer + theRegister + 1);
Uint32 Tleft1 = TregMemBuffer[theRegister + 2];
Uint32 TrightType = TregMemBuffer[TrightRegister];
Uint32 Tright0 = TregMemBuffer[TrightRegister + 1];
Uint32 Tright1 = TregMemBuffer[TrightRegister + 2];
if ((TrightType | TleftType) != 0) { if ((TrightType | TleftType) != 0) {
jam(); jam();
if ((Tleft0 > Tright0) || ((Tleft0 == Tright0) && if (Tleft0 > Tright0){
(Tleft1 > Tright1))) {
TprogramCounter = brancher(theInstruction, TprogramCounter); TprogramCounter = brancher(theInstruction, TprogramCounter);
}//if }//if
} else { } else {
...@@ -1823,17 +1798,16 @@ int Dbtup::interpreterNextLab(Signal* signal, ...@@ -1823,17 +1798,16 @@ int Dbtup::interpreterNextLab(Signal* signal,
{ {
Uint32 TrightRegister = Interpreter::getReg2(theInstruction) << 2; Uint32 TrightRegister = Interpreter::getReg2(theInstruction) << 2;
Uint32 TrightType = TregMemBuffer[TrightRegister];
Int64 Tright0 = * (Int64*)(TregMemBuffer + TrightRegister + 1);
Uint32 TleftType = TregMemBuffer[theRegister]; Uint32 TleftType = TregMemBuffer[theRegister];
Uint32 Tleft0 = TregMemBuffer[theRegister + 1]; Int64 Tleft0 = * (Int64*)(TregMemBuffer + theRegister + 1);
Uint32 Tleft1 = TregMemBuffer[theRegister + 2];
Uint32 TrightType = TregMemBuffer[TrightRegister];
Uint32 Tright0 = TregMemBuffer[TrightRegister + 1];
Uint32 Tright1 = TregMemBuffer[TrightRegister + 2];
if ((TrightType | TleftType) != 0) { if ((TrightType | TleftType) != 0) {
jam(); jam();
if ((Tleft0 > Tright0) || ((Tleft0 == Tright0) && if (Tleft0 >= Tright0){
(Tleft1 >= Tright1))) {
TprogramCounter = brancher(theInstruction, TprogramCounter); TprogramCounter = brancher(theInstruction, TprogramCounter);
}//if }//if
} else { } else {
......
ndb/src/ndbapi/Ndb.cpp
View file @ b62d2ac0
...@@ -859,15 +859,7 @@ Ndb::opTupleIdOnNdb(Uint32 aTableId, Uint64 opValue, Uint32 op) ...@@ -859,15 +859,7 @@ Ndb::opTupleIdOnNdb(Uint32 aTableId, Uint64 opValue, Uint32 op)
case 0: case 0:
tOperation->interpretedUpdateTuple(); tOperation->interpretedUpdateTuple();
tOperation->equal("SYSKEY_0", aTableId ); tOperation->equal("SYSKEY_0", aTableId );
{ tOperation->incValue("NEXTID", opValue);
#ifdef WORDS_BIGENDIAN
Uint64 cacheSize64 = opValue; // XXX interpreter bug on Uint32
tOperation->incValue("NEXTID", cacheSize64);
#else
Uint32 cacheSize32 = opValue; // XXX for little-endian
tOperation->incValue("NEXTID", cacheSize32);
#endif
}
tRecAttrResult = tOperation->getValue("NEXTID"); tRecAttrResult = tOperation->getValue("NEXTID");
if (tConnection->execute( Commit ) == -1 ) if (tConnection->execute( Commit ) == -1 )
......
ndb/src/ndbapi/NdbOperationInt.cpp
View file @ b62d2ac0
...@@ -408,9 +408,7 @@ NdbOperation::incValue(const NdbColumnImpl* tNdbColumnImpl, Uint64 aValue) ...@@ -408,9 +408,7 @@ NdbOperation::incValue(const NdbColumnImpl* tNdbColumnImpl, Uint64 aValue)
// Load aValue into register 7 // Load aValue into register 7
if (insertATTRINFO( Interpreter::LoadConst64(7)) == -1) if (insertATTRINFO( Interpreter::LoadConst64(7)) == -1)
goto incValue_error1; goto incValue_error1;
if (insertATTRINFO((Uint32)(aValue >> 32)) == -1) if (insertATTRINFOloop((Uint32*)&aValue, 2) == -1)
goto incValue_error1;
if (insertATTRINFO(Uint32(aValue & 0xFFFFFFFF)) == -1)
goto incValue_error1; goto incValue_error1;
// Add register 6 and 7 and put result in register 7 // Add register 6 and 7 and put result in register 7
if (insertATTRINFO( Interpreter::Add(7, 6, 7)) == -1) if (insertATTRINFO( Interpreter::Add(7, 6, 7)) == -1)
...@@ -451,9 +449,7 @@ NdbOperation::subValue(const NdbColumnImpl* tNdbColumnImpl, Uint64 aValue) ...@@ -451,9 +449,7 @@ NdbOperation::subValue(const NdbColumnImpl* tNdbColumnImpl, Uint64 aValue)
// Load aValue into register 7 // Load aValue into register 7
if (insertATTRINFO( Interpreter::LoadConst64(7)) == -1) if (insertATTRINFO( Interpreter::LoadConst64(7)) == -1)
goto subValue_error1; goto subValue_error1;
if (insertATTRINFO((Uint32)(aValue >> 32)) == -1) if (insertATTRINFOloop((Uint32*)&aValue, 2) == -1)
goto subValue_error1;
if (insertATTRINFO(Uint32(aValue & 0xFFFFFFFF)) == -1)
goto subValue_error1; goto subValue_error1;
// Subtract register 6 and 7 and put result in register 7 // Subtract register 6 and 7 and put result in register 7
if (insertATTRINFO( Interpreter::Sub(7, 6, 7)) == -1) if (insertATTRINFO( Interpreter::Sub(7, 6, 7)) == -1)
...@@ -690,8 +686,6 @@ int ...@@ -690,8 +686,6 @@ int
NdbOperation::load_const_u64(Uint32 RegDest, Uint64 Constant) NdbOperation::load_const_u64(Uint32 RegDest, Uint64 Constant)
{ {
INT_DEBUG(("load_const_u64 %u %llu", RegDest, Constant)); INT_DEBUG(("load_const_u64 %u %llu", RegDest, Constant));
Uint32 tTemp1;
Uint32 tTemp2;
if (initial_interpreterCheck() == -1) if (initial_interpreterCheck() == -1)
return -1; return -1;
if (RegDest >= 8) if (RegDest >= 8)
...@@ -699,15 +693,11 @@ NdbOperation::load_const_u64(Uint32 RegDest, Uint64 Constant) ...@@ -699,15 +693,11 @@ NdbOperation::load_const_u64(Uint32 RegDest, Uint64 Constant)
setErrorCodeAbort(4229); setErrorCodeAbort(4229);
return -1; return -1;
} }
tTemp1 = (Uint32)(Constant >> 32);
tTemp2 = (Uint32)(Constant & 0xFFFFFFFF);
// 64 bit value // 64 bit value
if (insertATTRINFO( Interpreter::LoadConst64(RegDest)) == -1) if (insertATTRINFO( Interpreter::LoadConst64(RegDest)) == -1)
return -1; return -1;
if (insertATTRINFO(tTemp1) == -1) if (insertATTRINFOloop((Uint32*)&Constant, 2) == -1)
return -1;
if (insertATTRINFO(tTemp2) == -1)
return -1; return -1;
theErrorLine++; theErrorLine++;
return 0; return 0;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7