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ORS Hardware
Commit 941ce1e0 authored by Yuanxiang PAN's avatar Yuanxiang PAN Committed by Thomas Gambier
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Change project name from "Ors" to "OrsTypeA"

parent cc53f776
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hardOrs/Project Outputs for Ors/BOM/macroLibreOffice.bas deleted 100644 → 0
View file @ cc53f776
sub FormatBomRapidSpace
rem ----------------------------------------------------------------------
rem define variables
dim document as object
dim dispatcher as object
rem ----------------------------------------------------------------------
rem get access to the document
document = ThisComponent.CurrentController.Frame
dispatcher = createUnoService("com.sun.star.frame.DispatchHelper")
rem ajuste la largeur de la colonne x au contenu des cellules en 1/10mm:
ThisComponent.Sheets(0).Columns(0).Width = 10000 rem Designator list
ThisComponent.Sheets(0).Columns(1).Width = 3700 rem FootPrint
ThisComponent.Sheets(0).Columns(2).Width = 4500 rem Manufacturer
ThisComponent.Sheets(0).Columns(3).Width = 5000 rem Type
ThisComponent.Sheets(0).Columns(4).Width = 3800 rem Value
ThisComponent.Sheets(0).Columns(5).Width = 1800 rem Qte
ThisComponent.Sheets(0).Columns(6).Width = 7000 rem Infos
rem ----------------------------------------------------------------------
dispatcher.executeDispatch(document, ".uno:SelectAll", "", 0, Array())
rem ----------------------------------------------------------------------
dim args2(2) as new com.sun.star.beans.PropertyValue
args2(0).Name = "FontHeight.Height"
args2(0).Value = 10
args2(1).Name = "FontHeight.Prop"
args2(1).Value = 100
args2(2).Name = "FontHeight.Diff"
args2(2).Value = 0
dispatcher.executeDispatch(document, ".uno:FontHeight", "", 0, args2())
rem ----------------------------------------------------------------------
dim args3(0) as new com.sun.star.beans.PropertyValue
args3(0).Name = "WrapText"
args3(0).Value = true
dispatcher.executeDispatch(document, ".uno:WrapText", "", 0, args3())
rem ---Figer les Volets----------------------------------------------------------
dim args1(0) as new com.sun.star.beans.PropertyValue
args1(0).Name = "ToPoint"
args1(0).Value = "$B$2"
dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args1())
dispatcher.executeDispatch(document, ".uno:FreezePanes", "", 0, Array())
rem ----------------------------------------------------------------------
dim args6(0) as new com.sun.star.beans.PropertyValue
args6(0).Name = "ToPoint"
args6(0).Value = "$A$2"
dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args6())
rem ----------------------------------------------------------------------
dim args5(0) as new com.sun.star.beans.PropertyValue
Dim oCurrentSelection As Variant
Dim oRows As Variant, oCols As Variant
args5(0).Name = "Sel"
args5(0).Value = true
dispatcher.executeDispatch(document, ".uno:GoToEndOfData", "", 0, args5())
oCurrentSelection = ThisComponent.getCurrentSelection()
oRows = oCurrentSelection.getRows()
oCols = oCurrentSelection.getColumns()
Dim oDocument As Object, oSheet As Object, oCell As Object
Dim l As Integer, pair As Integer, nbrCol As Integer,nbrRow As Integer
Dim strLayer As String, index As Integer, nbOccurences As Integer, oCell2 As Object
oDocument = ThisComponent
oSheet=oDocument.Sheets.getByName ("Feuille1" )
pair = 0
nbrCol = oCols.getCount()
nbrRow = oRows.getCount()
rem ----diplays Top or Bottom----------------------------------------
osheet = ThisComponent.CurrentController.ActiveSheet
For l = 1 To nbrRow
oCell2 = osheet.getCellByPosition(7, l)
strLayer = oCell2.getString()
oCell2.setString("")
index = InStr(strLayer, "Top")
if index > 0 then
oCell2 = osheet.getCellByPosition(7, l)
oCell2.setString("T")
endif
index = InStr(strLayer, "Bottom")
if index > 0 then
oCell2 = osheet.getCellByPosition(7, l)
oCell2.setString(oCell2.getString() +"B")
endif
Next l
For l = 1 To nbrRow
oCell = oSheet.getCellrangeByPosition(0,l,nbrCol-1,l)
if pair = 0 then
oCell.CellBackColor = RGB(245,245,245)
pair = 1
else
oCell.CellBackColor = RGB(250,240,230)
pair = 0
endif
Next l
oCell = oSheet.getCellrangeByPosition(0,0,nbrCol-1,nbrRow)
oCell.VERTJUSTIFY=com.sun.star.table.CellVertJustify.CENTER
oCell.HORIJUSTIFY=com.sun.star.table.CellHoriJustify.LEFT
rem Mise en form des enttes
oCell = oSheet.getCellrangeByPosition(0,0,nbrCol-1,0)
oCell.CharWeight = com.sun.star.awt.FontWeight.BOLD
oCell.HORIJUSTIFY=com.sun.star.table.CellHoriJustify.CENTER
rem semble faire un unselect
dispatcher.executeDispatch(document, ".uno:GoToCell", "", 0, args5())
end sub
\ No newline at end of file
hardOrs/Project Outputs for Ors/Ors.BOM deleted 100644 → 0
View file @ cc53f776
This diff is collapsed.
hardOrsTypeA/OrsTypeA.PrjPcbStructure 0 → 100644
View file @ 941ce1e0
Record=TopLevelDocument|FileName=OrsTypeA_Top.SchDoc
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeA_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=OrsTypeA_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Pwr_0.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeA_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeA_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Pwr_0.SchDoc|Designator=b|SchDesignator=b|FileName=OrsTypeA_Pwr_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeA_Pwr_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Pwr_0.SchDoc|Designator=b2|SchDesignator=b2|FileName=OrsTypeA_Pwr_2.SchDoc|SymbolType=Normal|RawFileName=OrsTypeA_Pwr_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeA_Supply_0.SchDoc|SymbolType=Normal|RawFileName=OrsTypeA_Supply_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsTypeA_Prog.SchDoc|SymbolType=Normal|RawFileName=OrsTypeA_Prog.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Top.SchDoc|Designator=root|SchDesignator=root|FileName=OrsTypeA_0.SchDoc; OrsTypeA_1.SchDoc; OrsTypeA_2.SchDoc; OrsTypeA_3.SchDoc; OrsTypeA_4.SchDoc; OrsTypeA_5.SchDoc; OrsTypeA_6.SchDoc; OrsTypeA_7.SchDoc; OrsTypeA_8.SchDoc; OrsTypeA_9.SchDoc;|SymbolType=Normal|RawFileName=OrsTypeA_0.SchDoc; OrsTypeA_1.SchDoc; OrsTypeA_2.SchDoc; OrsTypeA_3.SchDoc; OrsTypeA_4.SchDoc; OrsTypeA_5.SchDoc; OrsTypeA_6.SchDoc; OrsTypeA_7.SchDoc; OrsTypeA_8.SchDoc; OrsTypeA_9.SchDoc;|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Top.SchDoc|Designator=RxTxPower|SchDesignator=RxTxPower|FileName=OrsTypeA_Pwr_0.SchDoc|SymbolType=Normal|RawFileName=OrsTypeA_Pwr_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsTypeA_Top.SchDoc|Designator=U_LowPwrLTE1|SchDesignator=U_LowPwrLTE1|FileName=OrsTypeA_Supply_1.SchDoc|SymbolType=Normal|RawFileName=OrsTypeA_Supply_1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
hardOrsTypeA/Project Logs for OrsTypeA/OrsTypeA PCB ECO 5-4-2023 11-38-53 AM.LOG 0 → 100644
View file @ 941ce1e0
Change Component Comment : Designator=Q6 Old Comment=MOSFET_SMSi7232DN New Comment=MOSFET_SMDual NMOSFET
Change Class Name : Old Net Name=Ors_Prog New Net Name=OrsTypeA_Prog
Change Class Name : Old Net Name=Ors_Pwr_1 New Net Name=OrsTypeA_Pwr_1
Change Class Name : Old Net Name=Ors_Pwr_2 New Net Name=OrsTypeA_Pwr_2
Change Class Name : Old Net Name=Ors_Supply_0 New Net Name=OrsTypeA_Supply_0
Change Class Name : Old Net Name=Ors_Top New Net Name=OrsTypeA_Top
Added Class: Name=OrsTypeA_Pwr_1
Added Class: Name=OrsTypeA_Pwr_2
hardOrs/Project Outputs for Ors/Design Rule Check - Ors.drc → hardOrsTypeA/Project Outputs for OrsTypeA/Design Rule Check - OrsTypeA.drc
View file @ 941ce1e0
Protel Design System Design Rule Check
PCB File : Z:\ors-hardware\hardOrs\Ors.PcbDoc
Date : 2/6/2023
Time : 4:52:43 PM
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:01:34
\ No newline at end of file
Protel Design System Design Rule Check
PCB File : Z:\ors-hardware\hardOrs\OrsTypeA.PcbDoc
Date : 5/4/2023
Time : 11:39:04 AM
Processing Rule : Clearance Constraint (Gap=0.35mm) (InNetClass('HighIsolation')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('TOP-GND') OR InNamedPolygon('GND-BOTTOM_PWR1')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNetClass('50OhmsL8tol4')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (InNetClass('DiffPairNetClass')),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.6mm) (InNetClass('50OhmsL1toL2')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.21mm) (InNetClass('50OhmsL8toL5')),(InPolygon)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.12mm) (InNetClass('DiffPairNetClass100Ohms_1_2')),(InPolygon)
Rule Violations :0
Violations Detected : 0
Time Elapsed : 00:01:57
\ No newline at end of file
hardOrs/Project Outputs for Ors/Gerber/Gerber Files.EXTREP → hardOrsTypeA/Project Outputs for OrsTypeA/Gerber/Gerber Files.EXTREP
View file @ 941ce1e0
------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 4/27/2023 5:08:24 PM
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL TOP
.G1 L2
.G2 L3
.G3 L4
.G4 L5
.G5 L6
.G6 L7
.GBL BOTTOM
.GTO Top Overlay
.GTP Top Paste
.GTS Top Solder
.GBS Bottom Solder
.GBP Bottom Paste
.GBO Bottom Overlay
.GM1 Mechanical 1
.GM2 Mechanical 2
.GM3 Mechanical 3
.GM7 SOLE_EDGE-V4
.GM13 DIMENSION
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Gerber File Extension Report For: Gerber Files.GBR 5/4/2023 11:55:34 AM
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTL TOP
.G1 L2
.G2 L3
.G3 L4
.G4 L5
.G5 L6
.G6 L7
.GBL BOTTOM
.GTO Top Overlay
.GTP Top Paste
.GTS Top Solder
.GBS Bottom Solder
.GBP Bottom Paste
.GBO Bottom Overlay
.GM1 Mechanical 1
.GM2 Mechanical 2
.GM3 Mechanical 3
.GM7 SOLE_EDGE-V4
.GM13 DIMENSION
------------------------------------------------------------------------------------------
hardOrs/Project Outputs for Ors/Gerber/Gerber Files.RUL → hardOrsTypeA/Project Outputs for OrsTypeA/Gerber/Gerber Files.RUL
View file @ 941ce1e0
DRC Rules Export File for PCB: Z:\ors-hardware\hardOrs\Ors.PcbDoc
RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=HighIsolation|Scope=Board|Minimum=13.78
DRC Rules Export File for PCB: Z:\ors-hardware\hardOrsTypeA\OrsTypeA.PcbDoc
RuleKind=Clearance|RuleName=100OhmsL8toL1_2|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=50OhmsL8toL5|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=50OhmsL1toL2|Scope=Board|Minimum=23.62
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=1.97
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=3.94
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Clearance|RuleName=DiffPairNetClass|Scope=Board|Minimum=3.94
RuleKind=Clearance|RuleName=PolyGon PourClearance_NoNet|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=50OhmsL8toL4|Scope=Board|Minimum=19.69
RuleKind=Clearance|RuleName=PolyGon Pour Clearance_12V|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=Clearance-Via_1|Scope=Board|Minimum=4.72
RuleKind=Clearance|RuleName=PolyGon Clearance_GND|Scope=Board|Minimum=7.87
RuleKind=Clearance|RuleName=PolyGon Clearance_ALL|Scope=Board|Minimum=8.27
RuleKind=Clearance|RuleName=HighIsolation|Scope=Board|Minimum=13.78
hardOrs/Project Outputs for Ors/NC Drill/NC Drill Files-NonPlated.TXT → hardOrsTypeA/Project Outputs for OrsTypeA/NC Drill/NC Drill Files-NonPlated.TXT
View file @ 941ce1e0
M48
;Layer_Color=9474304
;FILE_FORMAT=4:3
METRIC,TZ
;TYPE=NON_PLATED
T7F00S00C1.000
%
T07
X325250Y204650
Y209350
X242150Y269900
X325255Y255805
Y251105
X325250Y243850
Y239150
X242150Y279900
M30
M48
;Layer_Color=9474304
;FILE_FORMAT=4:3
METRIC,TZ
;TYPE=NON_PLATED
T7F00S00C1.000
%
T07
X325250Y204650
Y209350
X242150Y269900
X325255Y255805
Y251105
X325250Y243850
Y239150
X242150Y279900
M30
hardOrs/Project Outputs for Ors/NC Drill/NC Drill Files.DRR → hardOrsTypeA/Project Outputs for OrsTypeA/NC Drill/NC Drill Files.DRR
View file @ 941ce1e0
---------------------------------------------------------------------------
NCDrill File Report For: Ors.PcbDoc 4/27/2023 5:08:31 PM
---------------------------------------------------------------------------
Layer Pair : TOP to BOTTOM
ASCII Plated RoundHoles File : NC Drill Files-Plated.TXT
ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 0.2mm (7.874mil) Round 2457 4531.77 mm (178.42 Inch)
T2 0.25mm (9.842mil) Round 1800 4646.86 mm (182.95 Inch)
T3 0.3mm (11.811mil) Round 224 991.63 mm (39.04 Inch)
T4 0.5mm (19.685mil) Round 34 306.23 mm (12.06 Inch)
T5 2.6mm (102.362mil) Round 17 650.39 mm (25.61 Inch)
T6 3.25mm (127.953mil) Round 4 35.10 mm (1.38 Inch)
T7 1mm (39.37mil) Round 8 NPTH 301.02 mm (11.85 Inch)
---------------------------------------------------------------------------
Totals 4544 11463.00 mm (451.30 Inch)
Total Processing Time (hh:mm:ss) : 00:00:01
---------------------------------------------------------------------------
NCDrill File Report For: OrsTypeA.PcbDoc 5/4/2023 11:55:44 AM
---------------------------------------------------------------------------
Layer Pair : TOP to BOTTOM
ASCII Plated RoundHoles File : NC Drill Files-Plated.TXT
ASCII Non-Plated RoundHoles File : NC Drill Files-NonPlated.TXT
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 0.2mm (7.874mil) Round 2457 4531.90 mm (178.42 Inch)
T2 0.25mm (9.842mil) Round 1800 4646.86 mm (182.95 Inch)
T3 0.3mm (11.811mil) Round 224 991.63 mm (39.04 Inch)
T4 0.5mm (19.685mil) Round 34 306.23 mm (12.06 Inch)
T5 2.6mm (102.362mil) Round 17 650.39 mm (25.61 Inch)
T6 3.25mm (127.953mil) Round 4 35.10 mm (1.38 Inch)
T7 1mm (39.37mil) Round 8 NPTH 301.02 mm (11.85 Inch)
---------------------------------------------------------------------------
Totals 4544 11463.13 mm (451.30 Inch)
Total Processing Time (hh:mm:ss) : 00:00:02
hardOrs/Project Outputs for Ors/NC Drill/NC Drill Files.LDP → hardOrsTypeA/Project Outputs for OrsTypeA/NC Drill/NC Drill Files.LDP
View file @ 941ce1e0
Layer Pairs Export File for PCB: Z:\ors-hardware\hardOrs\Ors.PcbDoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl
Layer Pairs Export File for PCB: Z:\ors-hardware\hardOrsTypeA\OrsTypeA.PcbDoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=nc drill files-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=nc drill files-nonplated.txt|LayerPairs=gtl,gbl
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