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Commit 45f89daa authored by Josua Mayer's avatar Josua Mayer
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add support for lx2160a cex6 internal evaluation board

parent e7d2de52
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patches/linux-LSDK-21.08/0074-phy-lynx-28g-add-support-for-specifying-unmanaged-la.patch 0 → 100644
View file @ 45f89daa
From 160ad4b60348b152b668700908541e51b62b803b Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 27 Aug 2023 14:55:49 +0200
Subject: [PATCH] phy: lynx-28g: add support for specifying unmanaged lanes
Some lanes migt be used for non-networking purposes such as PCI-Express.
Add new device-tree property "fsl,unmanaged-lanes" for passing a bitmask
of unmanaged lanes which the driver will not touch.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../devicetree/bindings/phy/fsl,lynx-28g.yaml | 6 ++++++
drivers/phy/freescale/phy-fsl-lynx-28g.c | 19 ++++++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
index 4d91e2f4f247..71ff57927e32 100644
--- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
@@ -20,6 +20,12 @@ properties:
"#phy-cells":
const: 1
+ fsl,unmanaged-lanes:
+ $ref: /schemas/types.yaml#definitions/uint8
+ description: Select which lanes not to touch via bitmask: 0 = managed by driver, 1 = unmanaged.
+ minimum: 0
+ maximum: 255
+
required:
- compatible
- reg
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 2152066f2dbc..7e088fa4efce 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -5,6 +5,7 @@
#include <linux/phy.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/workqueue.h>
#include <linux/workqueue.h>
@@ -644,7 +645,9 @@ static int lynx_28g_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct phy_provider *provider;
struct lynx_28g_priv *priv;
- int i;
+ struct fwnode_handle *fwnode;
+ int i, ret;
+ u32 unmanaged_lanes;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -655,12 +658,26 @@ static int lynx_28g_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
+ fwnode = dev_fwnode(dev);
+ if (fwnode && is_of_node(fwnode)) {
+ ret = of_property_read_u32(to_of_node(fwnode), "fsl,unmanaged-lanes", &unmanaged_lanes);
+ if (ret) {
+ dev_info(dev, "failed to read fsl,unmanaged-lanes property: %d\n", ret);
+ return ret;
+ }
+ }
+
lynx_28g_pll_read_configuration(priv);
for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
struct lynx_28g_lane *lane = &priv->lane[i];
struct phy *phy;
+ if (unmanaged_lanes & (1 << i)) {
+ dev_err(dev, "unmanaged lane %d!\n", i);
+ continue;
+ }
+
memset(lane, 0, sizeof(*lane));
phy = devm_phy_create(&pdev->dev, NULL, &lynx_28g_ops);
--
2.35.3
patches/mc-utils/0018-lx2160acex6-add-configuration-for-evaluation-board.patch 0 → 100644
View file @ 45f89daa
From 3ea2242f61fe139dfd9ff0c4845dac22a6d54a77 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 27 Aug 2023 12:48:53 +0200
Subject: [PATCH] lx2160acex6: add configuration for evaluation board
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpc.dts | 99 ++++
.../lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpl.dts | 520 ++++++++++++++++++
2 files changed, 619 insertions(+)
create mode 100644 config/lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpc.dts
create mode 100644 config/lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpl.dts
diff --git a/config/lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpc.dts b/config/lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpc.dts
new file mode 100644
index 0000000..3058e69
--- /dev/null
+++ b/config/lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpc.dts
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ resources {
+ icid_pools {
+ icid_pool@1 {
+ num = <0x64>;
+ base_icid = <0x0>;
+ };
+ };
+ };
+
+ mc_general {
+ log {
+ mode = "LOG_MODE_ON";
+ level = "LOG_LEVEL_WARNING";
+ };
+
+ console {
+ mode = "CONSOLE_MODE_OFF";
+ uart_id = <0x4>;
+ level = "LOG_LEVEL_WARNING";
+ };
+ };
+
+ controllers {
+ qbman {
+ /* Transform this number of 8-WQ channels into four times
+ * as many 2-WQ channels. This allows the creation of a
+ * larger number of DPCONs.
+ */
+ wq_ch_conversion = <64>;
+ };
+ };
+
+ board_info {
+ recycle_ports {
+ recycle@1 {
+ max_rate = "1G";
+ };
+
+ recycle@2 {
+ max_rate = "1G";
+ };
+ };
+
+ ports {
+ /* Serdes 1 */
+ mac@3 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@4 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@5 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ mac@6 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ /* WRIOP MAC */
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+ };
+ };
+};
diff --git a/config/lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpl.dts b/config/lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpl.dts
new file mode 100644
index 0000000..477cf1a
--- /dev/null
+++ b/config/lx2160a/LX2160-CEX6/evb-s1_3-s2-3-dpl.dts
@@ -0,0 +1,520 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2023 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+ dpl-version = <10>;
+ /*****************************************************************
+ * Containers
+ *****************************************************************/
+ containers {
+
+ dprc@1 {
+ compatible = "fsl,dprc";
+ parent = "none";
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+
+ objects {
+
+ /* -------------- DPBPs --------------*/
+ obj_set@dpbp {
+ type = "dpbp";
+ ids = <0 >;
+ };
+
+ /* -------------- DPCONs --------------*/
+ obj_set@dpcon {
+ type = "dpcon";
+ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >;
+ };
+
+ /* -------------- DPIOs --------------*/
+ obj_set@dpio {
+ type = "dpio";
+ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >;
+ };
+
+ /* -------------- DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <3 4 5 6 17 >;
+ };
+
+ /* -------------- DPMCPs --------------*/
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 >;
+ };
+
+ /* -------------- DPNIs --------------*/
+ obj_set@dpni {
+ type = "dpni";
+ ids = <0 >;
+ };
+ };
+ };
+ };
+
+ /*****************************************************************
+ * Objects
+ *****************************************************************/
+ objects {
+
+ dpbp@0 {
+ compatible = "fsl,dpbp";
+ };
+
+ dpcon@0 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@1 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@2 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@3 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@4 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@5 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@6 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@7 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@8 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@9 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@10 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@11 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@12 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@13 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@14 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@15 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpio@0 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@1 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@2 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@3 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@4 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@5 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@6 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@7 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@8 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@9 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@10 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@11 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@12 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@13 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@14 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpio@15 {
+ compatible = "fsl,dpio";
+ channel_mode = "DPIO_LOCAL_CHANNEL";
+ num_priorities = <0x8>;
+ };
+
+ dpmac@3 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac@4 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac@5 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac@6 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac@17 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmcp@1 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@2 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@3 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@4 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@5 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@6 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@7 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@8 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@9 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@10 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@11 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@12 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@13 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@14 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@15 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@16 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@17 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@18 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@19 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@20 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@21 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@22 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@23 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@24 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@25 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@26 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@27 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@28 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@29 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@30 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@31 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@32 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@33 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@34 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@35 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@36 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@37 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@38 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@39 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@40 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@41 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@42 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@43 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@44 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@45 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@46 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@47 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@48 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@49 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@50 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@51 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpmcp@52 {
+ compatible = "fsl,dpmcp";
+ };
+
+ dpni@0 {
+ compatible = "fsl,dpni";
+ type = "DPNI_TYPE_NIC";
+ num_queues = <16>;
+ num_tcs = <1>;
+ num_cgs = <1>;
+ mac_filter_entries = <16>;
+ vlan_filter_entries = <0>;
+ fs_entries = <64>;
+ qos_entries = <0>;
+ dist_key_size = <56>;
+ };
+ };
+
+ /*****************************************************************
+ * Connections
+ *****************************************************************/
+ connections {
+
+ connection@1{
+ endpoint1 = "dpni@0";
+ endpoint2 = "dpmac@17";
+ };
+ };
+};
--
2.35.3
patches/rcw-LSDK-21.08/0030-add-lx2160a-cex6-evb-configuration-3_3_2.patch 0 → 100644
View file @ 45f89daa
From fd36f76e50577fbf3f4bb3bc6fce3ce2ad91b0ae Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 27 Aug 2023 13:19:59 +0200
Subject: [PATCH] add lx2160a cex6 evb configuration 3_3_2
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
lx2160acex7/configs/lx2160acex6_evb.rcwi | 20 +++++++++++++++++++
.../configs/lx2160acex6_evb_SD1_3.rcwi | 18 +++++++++++++++++
.../configs/lx2160acex6_evb_SD2_3.rcwi | 18 +++++++++++++++++
.../configs/lx2160acex6_evb_SD3_2.rcwi | 18 +++++++++++++++++
4 files changed, 74 insertions(+)
create mode 100644 lx2160acex7/configs/lx2160acex6_evb.rcwi
create mode 100644 lx2160acex7/configs/lx2160acex6_evb_SD1_3.rcwi
create mode 100644 lx2160acex7/configs/lx2160acex6_evb_SD2_3.rcwi
create mode 100644 lx2160acex7/configs/lx2160acex6_evb_SD3_2.rcwi
diff --git a/lx2160acex7/configs/lx2160acex6_evb.rcwi b/lx2160acex7/configs/lx2160acex6_evb.rcwi
new file mode 100644
index 0000000..9daf8fd
--- /dev/null
+++ b/lx2160acex7/configs/lx2160acex6_evb.rcwi
@@ -0,0 +1,20 @@
+/* Configure Ethernet Controller 2 Pins as GPIOs */
+EC2_PMUX=1
+
+/* Configure IIC4 for i2c */
+IIC4_PMUX=0
+
+/* Configure IIC5 for spi */
+IIC5_PMUX=3
+
+/* Configure UART1 for uart-1 */
+UART1_SOUTSIN_PMUX=0
+
+/* Configure UART1 RTS/CTS for uart-3
+UART1_RTSCTS_PMUX=2
+
+/* Configure UART2 for uart-2 */
+UART2_SOUTSIN_PMUX=0
+
+/* Configure UART1 RTS/CTS for uart-4 */
+UART2_RTSCTS_PMUX=2
diff --git a/lx2160acex7/configs/lx2160acex6_evb_SD1_3.rcwi b/lx2160acex7/configs/lx2160acex6_evb_SD1_3.rcwi
new file mode 100644
index 0000000..7f5f35f
--- /dev/null
+++ b/lx2160acex7/configs/lx2160acex6_evb_SD1_3.rcwi
@@ -0,0 +1,18 @@
+/* Serdes 1 Protocol 3: 4x10Gbps + 1xPCI-e-x4 */
+SRDS_PRTCL_S1=3
+
+/* Enable Serdes 1 PLLF */
+SRDS_PLL_PD_PLL1=0
+
+/* Don't use Serdes 1 PLLF for PLLS */
+SRDS_INTRA_REF_CLK_S1=0
+
+/* Enable Serdes 1 PLLS */
+SRDS_PLL_PD_PLL2=0
+
+/*
+ * Select Serdes 1 PLLF frequency 100MHz for pcie: Bit 0 = 0
+ * Select Serdes 1 PLLS frequency 161.1328125MHz (not documented in RM) for usxgmii: Bit 1 = 1
+ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
+ */
+SRDS_PLL_REF_CLK_SEL_S1=2
diff --git a/lx2160acex7/configs/lx2160acex6_evb_SD2_3.rcwi b/lx2160acex7/configs/lx2160acex6_evb_SD2_3.rcwi
new file mode 100644
index 0000000..d5f2acb
--- /dev/null
+++ b/lx2160acex7/configs/lx2160acex6_evb_SD2_3.rcwi
@@ -0,0 +1,18 @@
+/* Serdes 2 Protocol 3: 2xPCI-e-x4 */
+SRDS_PRTCL_S2=3
+
+/* Enable Serdes 2 PLLF */
+SRDS_PLL_PD_PLL3=0
+
+/* Don't use Serdes 2 PLLF for PLLS */
+SRDS_INTRA_REF_CLK_S2=0
+
+/* Enable Serdes 2 PLLS */
+SRDS_PLL_PD_PLL4=0
+
+/*
+ * Select Serdes 2 PLLF frequency 100MHz (Bit 0)
+ * Select Serdes 2 PLLS frequency 100MHz (Bit 1)
+ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
+ */
+SRDS_PLL_REF_CLK_SEL_S2=0
diff --git a/lx2160acex7/configs/lx2160acex6_evb_SD3_2.rcwi b/lx2160acex7/configs/lx2160acex6_evb_SD3_2.rcwi
new file mode 100644
index 0000000..568fa4d
--- /dev/null
+++ b/lx2160acex7/configs/lx2160acex6_evb_SD3_2.rcwi
@@ -0,0 +1,18 @@
+/* Serdes 3 Protocol 2: 1xPCI-e-x8 */
+SRDS_PRTCL_S3=2
+
+/* Disable Serdes 3 PLLF */
+SRDS_PLL_PD_PLL5=1
+
+/* Don't use Serdes 3 PLLF as reference for PLLS */
+SRDS_INTRA_REF_CLK_S3=0
+
+/* Enable Serdes 3 PLLS */
+SRDS_PLL_PD_PLL6=0
+
+/*
+ * Select Serdes 2 PLLF frequency 100MHz (don't care) (Bit 0)
+ * Select Serdes 2 PLLS frequency 100MHz for pcie (Bit 1)
+ * (See QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
+ */
+SRDS_PLL_REF_CLK_SEL_S3=0
--
2.35.3
runme.sh
View file @ 45f89daa
...@@ -132,6 +132,11 @@ case "${SERDES}" in ...@@ -132,6 +132,11 @@ case "${SERDES}" in
DPC=dpc-6x25g.dtb DPC=dpc-6x25g.dtb
DPL=dpl-eth.6x25g.21.dtb DPL=dpl-eth.6x25g.21.dtb
;; ;;
LX2160ACEX6_EVB_3_3_2)
DPC=LX2160-CEX6/evb-s1_3-s2-3-dpc.dtb
DPL=LX2160-CEX6/evb-s1_3-s2-3-dpl.dtb
DEFAULT_FDT_FILE="fsl-lx2160a-cex6.dtb"
;;
LX2162A_CLEARFOG_0_0_*) LX2162A_CLEARFOG_0_0_*)
DPC=LX2162-USOM/clearfog-s1_0-s2_0-dpc.dtb DPC=LX2162-USOM/clearfog-s1_0-s2_0-dpc.dtb
DPL=LX2162-USOM/clearfog-s1_0-s2_0-dpl.dtb DPL=LX2162-USOM/clearfog-s1_0-s2_0-dpl.dtb
......
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