Commit 67165049 authored by Rabeeh Khoury's avatar Rabeeh Khoury

backport of the usb 3.0 designware parkmode workaround

Signed-off-by: default avatarRabeeh Khoury <rabeeh@solid-run.com>
parent ccce7bb0
From 2ce0d3a0c1e218d6e680115da21a0e9c180db845 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 28 Oct 2020 20:06:16 +0200
Subject: [PATCH] usb: dwc3: core: add support for disabling SS instances in
park mode
This is a backport from mainline -
commit 7ba6b09fda5e0cb741ee56f3264665e0edc64822
Author: Neil Armstrong <narmstrong@baylibre.com>
Date: Fri Feb 21 10:15:31 2020 +0100
usb: dwc3: core: add support for disabling SS instances in park mode
In certain circumstances, the XHCI SuperSpeed instance in park mode
In certain circumstances, the XHCI SuperSpeed instance in park mode
can fail to recover, thus on Amlogic G12A/G12B/SM1 SoCs when there is high
load on the single XHCI SuperSpeed instance, the controller can crash like:
xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
......@@ -14,18 +19,18 @@ Date: Fri Feb 21 10:15:31 2020 +0100
hub 2-1.1:1.0: hub_ext_port_status failed (err = -22)
xhci-hcd xhci-hcd.0.auto: HC died; cleaning up
usb 2-1.1-port1: cannot reset (err = -22)
Setting the PARKMODE_DISABLE_SS bit in the DWC3_USB3_GUCTL1 mitigates
the issue. The bit is described as :
"When this bit is set to '1' all SS bus instances in park mode are disabled"
Synopsys explains:
The GUCTL1.PARKMODE_DISABLE_SS is only available in
dwc_usb3 controller running in host mode.
This should not be set for other IPs.
This can be disabled by default based on IP, but I recommend to have a
property to enable this feature for devices that need this.
CC: Dongjin Kim <tobetter@gmail.com>
Cc: Jianxin Pan <jianxin.pan@amlogic.com>
Cc: Thinh Nguyen <thinhn@synopsys.com>
......@@ -34,11 +39,38 @@ Date: Fri Feb 21 10:15:31 2020 +0100
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
drivers/usb/dwc3/core.c | 5 +++++
drivers/usb/dwc3/core.h | 4 ++++
3 files changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index fe9b8bf4d..201bc2292 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -994,6 +994,7 @@
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
+ snps,parkmode-disable-ss-quirk;
dma-coherent;
status = "disabled";
};
@@ -1009,6 +1010,7 @@
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
snps,host-vbus-glitches;
+ snps,parkmode-disable-ss-quirk;
status = "disabled";
};
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 1d85c42b9c67..43bd5b1ea9e2 100644
index 5ed5a57f3..870f9cb14 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1029,6 +1029,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
@@ -1064,6 +1064,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (dwc->dis_tx_ipgap_linecheck_quirk)
reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
......@@ -48,7 +80,7 @@ index 1d85c42b9c67..43bd5b1ea9e2 100644
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
}
@@ -1342,6 +1345,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
@@ -1400,6 +1403,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
"snps,dis-del-phy-power-chg-quirk");
dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
"snps,dis-tx-ipgap-linecheck-quirk");
......@@ -58,18 +90,18 @@ index 1d85c42b9c67..43bd5b1ea9e2 100644
dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
"snps,tx_de_emphasis_quirk");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 77c4a9abe365..3ecc69c5b150 100644
index 1ea3c50d2..63f0b5fb3 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -249,6 +249,7 @@
@@ -266,6 +266,7 @@
#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
/* Global User Control 1 Register */
+#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
@@ -1024,6 +1025,8 @@ struct dwc3_scratchpad_array {
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
@@ -1041,6 +1042,8 @@ struct dwc3_scratchpad_array {
* change quirk.
* @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
* check during HS transmit.
......@@ -78,7 +110,7 @@ index 77c4a9abe365..3ecc69c5b150 100644
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
* @tx_de_emphasis: Tx de-emphasis value
* 0 - -6dB de-emphasis
@@ -1215,6 +1218,7 @@ struct dwc3 {
@@ -1236,6 +1239,7 @@ struct dwc3 {
unsigned dis_u2_freeclk_exists_quirk:1;
unsigned dis_del_phy_power_chg_quirk:1;
unsigned dis_tx_ipgap_linecheck_quirk:1;
......@@ -86,3 +118,6 @@ index 77c4a9abe365..3ecc69c5b150 100644
unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2;
--
2.25.1
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