LSDK-19.09 u-boot support

u-boot patches split into lsdk-19.06 and lsdk-19.09 and added patch
0015-.... that adds the support to lsdk-19.09.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>

patches/u-boot-LSDK-19.09/0001-armv8-add-lx2160acex7-build-inclusion.patch

+From 94e3a159d46ffb7f3e3186486dd74293cc33326f Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:26:45 +0300
+Subject: [PATCH 1/6] armv8: add lx2160acex7 build inclusion
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/Kconfig           | 13 +++++++++++++
+ arch/arm/cpu/armv8/Kconfig |  2 +-
+ arch/arm/dts/Makefile      |  3 ++-
+ 3 files changed, 16 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 958d048971..d439d42a4a 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1101,6 +1101,18 @@ config TARGET_LX2160ARDB
+ 	  is a high-performance development platform that supports the
+ 	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+ 
++config TARGET_LX2160ACEX7
++	bool "Support lx2160acex7"
++	select ARCH_LX2160A
++	select ARCH_MISC_INIT
++	select ARM64
++	select ARMV8_MULTIENTRY
++	select BOARD_LATE_INIT
++	help
++	  Support for SolidRun LX2160A based com express type 7 module and
++	  platform. The lx2160acex7 high-performance platform that supports the
++	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
++
+ config TARGET_LX2160AQDS
+ 	bool "Support lx2160aqds"
+ 	select ARCH_LX2160A
+@@ -1635,6 +1647,7 @@ source "board/freescale/ls1012aqds/Kconfig"
+ source "board/freescale/ls1012ardb/Kconfig"
+ source "board/freescale/ls1012afrdm/Kconfig"
+ source "board/freescale/lx2160a/Kconfig"
++source "board/solidrun/lx2160a/Kconfig"
+ source "board/freescale/mx35pdk/Kconfig"
+ source "board/freescale/s32v234evb/Kconfig"
+ source "board/grinn/chiliboard/Kconfig"
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index 92a2b58ed4..9df6ebdc1b 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -109,7 +109,7 @@ config PSCI_RESET
+ 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
+ 		   !TARGET_LS1046AFRWY && \
+ 		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
+-		   !TARGET_LX2160AQDS && \
++		   !TARGET_LX2160AQDS && !TARGET_LX2160ACEX7 && \
+ 		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
+ 	help
+ 	  Most armv8 systems have PSCI support enabled in EL3, either through
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index b9f34113ea..c5be9a52cc 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -298,7 +298,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ 	fsl-ls1088a-rdb.dtb \
+ 	fsl-ls1088a-qds.dtb \
+ 	fsl-lx2160a-rdb.dtb \
+-	fsl-lx2160a-qds.dtb
++	fsl-lx2160a-qds.dtb \
++	fsl-lx2160a-cex7.dtb
+ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+ 	fsl-ls1043a-qds-lpuart.dtb \
+ 	fsl-ls1043a-rdb.dtb \
+-- 
+2.17.1
+

patches/u-boot-LSDK-19.09/0002-armv8-lx2160acex-misc-hacks-to-get-the-sources-built.patch

+From dc622cf48bed312045d6a7762d166803db28dff3 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:27:46 +0300
+Subject: [PATCH 2/6] armv8: lx2160acex: misc hacks to get the sources built
+
+those hacks will be sorted out nicer in the future and this patch will
+not be needed anymore
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 -
+ drivers/mmc/fsl_esdhc.c                   | 2 +-
+ include/configs/lx2160a_common.h          | 4 ++--
+ 3 files changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+index 8c47d81f7f..9236be05c8 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
++++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+@@ -225,7 +225,6 @@ config ARCH_LX2160A
+ 	select SYS_FSL_DDR_LE
+ 	select SYS_FSL_DDR_VER_50
+ 	select SYS_FSL_EC1
+-	select SYS_FSL_EC2
+ 	select SYS_FSL_ERRATUM_A050106
+ 	select SYS_FSL_HAS_RGMII
+ 	select SYS_FSL_HAS_SEC
+diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
+index 53277c9216..1ec74bd6ba 100644
+--- a/drivers/mmc/fsl_esdhc.c
++++ b/drivers/mmc/fsl_esdhc.c
+@@ -1497,7 +1497,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
+ #endif
+ 	}
+ 
+-	priv->wp_enable = 1;
++	priv->wp_enable = 0;
+ 
+ #ifdef CONFIG_DM_GPIO
+ 	ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index e18c8dfd57..4549be92ab 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -248,8 +248,8 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	BOOTENV					\
+ 	"mcmemsize=0x70000000\0"		\
+ 	XSPI_MC_INIT_CMD				\
+-	"boot_scripts=lx2160ardb_boot.scr\0"	\
+-	"boot_script_hdr=hdr_lx2160ardb_bs.out\0"	\
++	"boot_scripts=lx2160acex7_boot.scr\0"	\
++	"boot_script_hdr=hdr_lx2160acex7_bs.out\0"	\
+ 	"scan_dev_for_boot_part="		\
+ 		"part list ${devtype} ${devnum} devplist; "	\
+ 		"env exists devplist || setenv devplist 1; "	\
+-- 
+2.17.1
+

patches/u-boot-LSDK-19.09/0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch

+From 62af256d25d61136913a739b14452b6d35eff3dc Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:29:31 +0300
+Subject: [PATCH 3/6] armv8: lx2160acex7: defconfig and main platform include
+
+This patch add lx2160acex7 main defconfig and main include file.
+Notice that the defconfig doesn't support the secured boot mode where a
+follow up patch will cover this.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ configs/lx2160acex7_tfa_defconfig | 73 ++++++++++++++++++++++++++
+ include/configs/lx2160acex7.h     | 85 +++++++++++++++++++++++++++++++
+ 2 files changed, 158 insertions(+)
+ create mode 100644 configs/lx2160acex7_tfa_defconfig
+ create mode 100644 include/configs/lx2160acex7.h
+
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+new file mode 100644
+index 0000000000..d59de7d054
+--- /dev/null
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -0,0 +1,73 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LX2160ACEX7=y
++CONFIG_SYS_TEXT_BASE=0x82000000
++CONFIG_SYS_MALLOC_F_LEN=0x6000
++CONFIG_EMC2301=y
++CONFIG_TFABOOT=y
++CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
++CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
++CONFIG_AHCI=y
++CONFIG_NR_DRAM_BANKS=3
++CONFIG_FIT_VERBOSE=y
++CONFIG_OF_BOARD_SETUP=y
++CONFIG_OF_BOARD_FIXUP=y
++CONFIG_OF_STDOUT_VIA_ALIAS=y
++CONFIG_BOOTDELAY=10
++CONFIG_USE_BOOTARGS=y
++CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
++# CONFIG_USE_BOOTCOMMAND is not set
++CONFIG_CMD_GREPENV=y
++CONFIG_CMD_EEPROM=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_SF=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_CACHE=y
++CONFIG_MP=y
++CONFIG_OF_CONTROL=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_IS_IN_SPI_FLASH=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_DM=y
++CONFIG_SATA_CEVA=y
++CONFIG_FSL_CAAM=y
++CONFIG_DM_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_SPANSION=y
++CONFIG_SPI_FLASH_STMICRO=y
++CONFIG_SPI_FLASH_MICRON=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_PHYLIB=y
++CONFIG_NETDEVICES=y
++CONFIG_PHY_GIGE=y
++CONFIG_CMD_NET=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_EXT2=y
++CONFIG_PCI=y
++CONFIG_DM_PCI=y
++CONFIG_DM_PCI_COMPAT=y
++CONFIG_PCIE_LAYERSCAPE_GEN4=y
++CONFIG_PHY_ATHEROS=y
++CONFIG_E1000=y
++CONFIG_DM_SCSI=y
++CONFIG_DM_SERIAL=y
++CONFIG_SERIAL_PROBE_ALL=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_NXP_FSPI=y
++# CONFIG_SYS_NXP_FSPI_AHB=y
++CONFIG_USB=y
++CONFIG_DM_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+new file mode 100644
+index 0000000000..478cd8242f
+--- /dev/null
++++ b/include/configs/lx2160acex7.h
+@@ -0,0 +1,85 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2019 SolidRun ltd.
++ */
++
++#ifndef __LX2_CEX7_H
++#define __LX2_CEX7_H
++
++#include "lx2160a_common.h"
++
++/*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/
++/* VID */
++
++#define I2C_MUX_CH_VOL_MONITOR		0x2
++/* Voltage monitor on channel 2*/
++#define I2C_VOL_MONITOR_ADDR		0x5c
++#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
++#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
++#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
++#define CONFIG_VID_FLS_ENV		"lx2160acex7_vdd_mv"
++#define CONFIG_VID
++
++/* The lowest and highest voltage allowed*/
++#define VDD_MV_MIN			700
++#define VDD_MV_MAX			855
++
++/* PM Bus commands code for LTC3882*/
++#define PMBUS_CMD_PAGE                  0x0
++#define PMBUS_CMD_READ_VOUT             0x8B
++#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
++#define PMBUS_CMD_VOUT_COMMAND          0x21
++#define PWM_CHANNEL0                    0x0
++
++#define CONFIG_VOL_MONITOR_LTC3882_SET
++#define CONFIG_VOL_MONITOR_LTC3882_READ
++
++/* RTC */
++#define CONFIG_SYS_RTC_BUS_NUM		4
++
++/* MAC/PHY configuration */
++#if defined(CONFIG_FSL_MC_ENET)
++#define CONFIG_MII
++#define CONFIG_ETHPRIME		"DPMAC17@rgmii-id"
++
++#define RGMII_PHY_ADDR1		0x01
++
++#endif
++
++/* EMC2301 */
++#define I2C_MUX_CH_EMC2301	0x01
++#define I2C_EMC2301_ADDR	0x2f
++#define I2C_EMC2301_CMD		0x40
++#define I2C_EMC2301_PWM		0x80
++
++/* EEPROM */
++#undef CONFIG_ID_EEPROM /* Fixme */
++#define CONFIG_SYS_I2C_EEPROM_NXID
++#define CONFIG_SYS_EEPROM_BUS_NUM	           0
++#define CONFIG_SYS_I2C_EEPROM_ADDR	           0x57
++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	    1
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
++
++/* Initial environment variables */
++#define CONFIG_EXTRA_ENV_SETTINGS		\
++	EXTRA_ENV_SETTINGS			\
++	"lx2160acex7_vdd_mv=800\0"		\
++	"BOARD=lx2160acex7\0"			\
++	"xspi_bootcmd=echo Trying load from flexspi..;"		\
++		"sf probe 0:0 && sf read $load_addr "		\
++		"$kernel_start $kernel_size ; env exists secureboot &&"	\
++		"sf read $kernelheader_addr_r $kernelheader_start "	\
++		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
++		" bootm $load_addr#$BOARD\0"			\
++	"sd_bootcmd=echo Trying load from sd card..;"		\
++		"mmcinfo; mmc read $load_addr "			\
++		"$kernel_addr_sd $kernel_size_sd ;"		\
++		"env exists secureboot && mmc read $kernelheader_addr_r "\
++		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
++		" && esbc_validate ${kernelheader_addr_r};"	\
++		"bootm $load_addr#$BOARD\0"
++
++#include <asm/fsl_secure_boot.h>
++
++#endif /* __LX2_CEX7_H */
+-- 
+2.17.1
+

patches/u-boot-LSDK-19.09/0005-armv8-lx2160acex7-lx2160acex-device-tree.patch

+From f8ac0b82bf2af732251419f05b9058e78ca2dbec Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:37:22 +0300
+Subject: [PATCH 5/6] armv8: lx2160acex7: lx2160acex device tree
+
+Based on NXP's LX2160ARDB device tree; it defines -
+1. MX35X based SPI flash
+2. SDHC0 (SD card) and SDHC1 (eMMC)
+3. 4 SATA ports that depending on SERDES configuration they can get
+connected to external SATA drives
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a-cex7.dts | 63 +++++++++++++++++++++++++++++++
+ 1 file changed, 63 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dts
+
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
+new file mode 100644
+index 0000000000..4fbcaafb0e
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
+@@ -0,0 +1,63 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * SolidRun LX2160ACEX7 device tree source
++ *
++ * Author:	Rabeeh Khoury <rabeeh@solid-run.com>
++ *
++ * Copyright 2019 SolidRun ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++
++/ {
++	model = "SolidRun LX2160ACEX7 COM express type 7 based board";
++	compatible = "fsl,lx2160acex7", "fsl,lx2160a";
++
++	aliases {
++		spi0 = &fspi;
++	};
++};
++
++&fspi {
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: MT35XU512ABA1G12@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "spi-flash";
++		spi-max-frequency = <50000000>;
++		reg = <0>;
++		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++		fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
++		fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
++	};
++
++};
++
++&esdhc0 {
++	status = "okay";
++};
++
++&esdhc1 {
++	status = "okay";
++};
++
++&sata0 {
++	status = "okay";
++};
++
++&sata1 {
++	status = "okay";
++};
++
++&sata2 {
++	status = "okay";
++};
++
++&sata3 {
++	status = "okay";
++};
+-- 
+2.17.1
+

patches/u-boot-LSDK-19.09/0007-load-dpl-into-0x80001000-instead-of-0x80d00000.patch

+From 322adff2224db26230ed23a1d84f335abecacfef Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 23 Oct 2019 15:03:25 +0300
+Subject: [PATCH 7/7] load dpl into 0x80001000 instead of 0x80d00000
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ include/configs/lx2160a_common.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index 4549be92ab..34cc29685d 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -279,11 +279,11 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 
+ #define SD_BOOTCOMMAND						\
+ 		"env exists mcinitcmd && mmcinfo; "		\
+-		"mmc read 0x80d00000 0x6800 0x800; "		\
++		"mmc read 0x80001000 0x6800 0x800; "		\
+ 		"env exists mcinitcmd && env exists secureboot "	\
+ 		" && mmc read 0x80780000 0x3C00 0x20 "		\
+ 		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+-		"&& fsl_mc lazyapply dpl 0x80d00000;"		\
++		"&& fsl_mc lazyapply dpl 0x80001000;"		\
+ 		"run distro_bootcmd;run sd_bootcmd;"		\
+ 		"env exists secureboot && esbc_halt;"
+ 
+-- 
+2.17.1
+

patches/u-boot-LSDK-19.09/0008-uboot-add-nvme-commands-and-for-distroboot.patch

+From a1fddcaae71a95bd4b9963c9000b9c88b6d152d5 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 11 Nov 2019 23:45:31 +0200
+Subject: [PATCH] uboot - add nvme commands and for distroboot
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ configs/lx2160acex7_tfa_defconfig | 2 ++
+ include/configs/lx2160a_common.h  | 3 ++-
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index d59de7d054..3891d2a7c4 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -25,6 +25,8 @@ CONFIG_CMD_PCI=y
+ CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_CACHE=y
++CONFIG_CMD_NVME=y
++CONFIG_NVME=y
+ CONFIG_MP=y
+ CONFIG_OF_CONTROL=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index 34cc29685d..7c2d749a9e 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -290,7 +290,8 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ #define BOOT_TARGET_DEVICES(func) \
+ 	func(USB, usb, 0) \
+ 	func(MMC, mmc, 0) \
+-	func(SCSI, scsi, 0)
++	func(SCSI, scsi, 0) \
++	func(NVME, nvme, 0)
+ #include <config_distro_bootcmd.h>
+ 
+ #endif /* __LX2_COMMON_H */
+-- 
+2.17.1
+

patches/u-boot-LSDK-19.09/0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch

+From aaa77bef5143ec037bd31477d482a68e10bfee1d Mon Sep 17 00:00:00 2001
+From: Damjan Marion <dmarion@me.com>
+Date: Thu, 21 Nov 2019 19:45:13 +0100
+Subject: [PATCH] armv8: lx2160acex7: Fix booting from NVMe drives
+
+Currently NVMe is not initialized so u-boot fails to read kernel from
+NVMe drive. This patch modifies default environment so it initializes
+NVMe as part of default startup script...
+
+Signed-off-by: Damjan Marion <dmarion@me.com>
+---
+ include/configs/lx2160a_common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index 4549be9..f4a4064 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -250,6 +250,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	XSPI_MC_INIT_CMD				\
+ 	"boot_scripts=lx2160acex7_boot.scr\0"	\
+ 	"boot_script_hdr=hdr_lx2160acex7_bs.out\0"	\
++	"nvme_need_init=true\0"	\
+ 	"scan_dev_for_boot_part="		\
+ 		"part list ${devtype} ${devnum} devplist; "	\
+ 		"env exists devplist || setenv devplist 1; "	\
+-- 
+2.20.1
+

patches/u-boot-LSDK-19.09/0010-nvme-Fix-warning-of-cast-from-pointer-to-integer-of-.patch

+From bd424e17884a25848ef858695133f773873c818c Mon Sep 17 00:00:00 2001
+From: Bin Meng <bmeng.cn@gmail.com>
+Date: Wed, 15 May 2019 08:37:56 -0700
+Subject: [PATCH 1/5] nvme: Fix warning of cast from pointer to integer of
+ different size
+
+When dma_addr_t is u32 in 64-bit, there are some warnings when
+building NVME driver. Fix it by doing an additional (long) cast.
+
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+(cherry picked from commit 5b2a20e9564c46a571126275991426dd8618e2d8)
+Signed-off-by: Olof Johansson <olof@lixom.net>
+---
+ drivers/nvme/nvme.c      | 4 ++--
+ drivers/nvme/nvme_show.c | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
+index 1ee0a0aefb..d4965e2ef6 100644
+--- a/drivers/nvme/nvme.c
++++ b/drivers/nvme/nvme.c
+@@ -577,7 +577,7 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev)
+ 	int ret;
+ 	int shift = NVME_CAP_MPSMIN(dev->cap) + 12;
+ 
+-	ret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl);
++	ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl);
+ 	if (ret)
+ 		return -EIO;
+ 
+@@ -646,7 +646,7 @@ static int nvme_blk_probe(struct udevice *udev)
+ 	ns->dev = ndev;
+ 	/* extract the namespace id from the block device name */
+ 	ns->ns_id = trailing_strtol(udev->name) + 1;
+-	if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)id))
++	if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id))
+ 		return -EIO;
+ 
+ 	flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
+diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c
+index 395b0618e6..15e459da1a 100644
+--- a/drivers/nvme/nvme_show.c
++++ b/drivers/nvme/nvme_show.c
+@@ -111,14 +111,14 @@ int nvme_print_info(struct udevice *udev)
+ 	ALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl));
+ 	struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl;
+ 
+-	if (nvme_identify(dev, 0, 1, (dma_addr_t)ctrl))
++	if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl))
+ 		return -EIO;
+ 
+ 	print_optional_admin_cmd(le16_to_cpu(ctrl->oacs), ns->devnum);
+ 	print_optional_nvm_cmd(le16_to_cpu(ctrl->oncs), ns->devnum);
+ 	print_format_nvme_attributes(ctrl->fna, ns->devnum);
+ 
+-	if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)id))
++	if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id))
+ 		return -EIO;
+ 
+ 	print_formats(id, ns);
+-- 
+2.22.GIT
+

patches/u-boot-LSDK-19.09/0011-nvme-Fix-PRP-Offset-Invalid.patch

+From 8c131511be5c0966c32989b1bf802951a783e1b0 Mon Sep 17 00:00:00 2001
+From: Aaron Williams <awilliams@marvell.com>
+Date: Thu, 22 Aug 2019 20:37:26 -0700
+Subject: [PATCH 2/5] nvme: Fix PRP Offset Invalid
+
+When large writes take place I saw a Samsung EVO 970+ return a status
+value of 0x13, PRP Offset Invalid.  I tracked this down to the
+improper handling of PRP entries.  The blocks the PRP entries are
+placed in cannot cross a page boundary and thus should be allocated
+on page boundaries.  This is how the Linux kernel driver works.
+
+With this patch, the PRP pool is allocated on a page boundary and
+other than the very first allocation, the pool size is a multiple of
+the page size.  Each page can hold (4096 / 8) - 1 entries since the
+last entry must point to the next page in the pool.
+
+Signed-off-by: Aaron Williams <awilliams@marvell.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+(cherry picked from commit b21dcebfa6b372cd91bf42a30f1d8a1a525f329b)
+Signed-off-by: Olof Johansson <olof@lixom.net>
+---
+ drivers/nvme/nvme.c | 29 +++++++++++++++++++----------
+ 1 file changed, 19 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
+index d4965e2ef6..47f101e280 100644
+--- a/drivers/nvme/nvme.c
++++ b/drivers/nvme/nvme.c
+@@ -73,6 +73,9 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
+ 	u64 *prp_pool;
+ 	int length = total_len;
+ 	int i, nprps;
++	u32 prps_per_page = (page_size >> 3) - 1;
++	u32 num_pages;
++
+ 	length -= (page_size - offset);
+ 
+ 	if (length <= 0) {
+@@ -89,15 +92,20 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
+ 	}
+ 
+ 	nprps = DIV_ROUND_UP(length, page_size);
++	num_pages = DIV_ROUND_UP(nprps, prps_per_page);
+ 
+ 	if (nprps > dev->prp_entry_num) {
+ 		free(dev->prp_pool);
+-		dev->prp_pool = malloc(nprps << 3);
++		/*
++		 * Always increase in increments of pages.  It doesn't waste
++		 * much memory and reduces the number of allocations.
++		 */
++		dev->prp_pool = memalign(page_size, num_pages * page_size);
+ 		if (!dev->prp_pool) {
+ 			printf("Error: malloc prp_pool fail\n");
+ 			return -ENOMEM;
+ 		}
+-		dev->prp_entry_num = nprps;
++		dev->prp_entry_num = prps_per_page * num_pages;
+ 	}
+ 
+ 	prp_pool = dev->prp_pool;
+@@ -788,14 +796,6 @@ static int nvme_probe(struct udevice *udev)
+ 	}
+ 	memset(ndev->queues, 0, NVME_Q_NUM * sizeof(struct nvme_queue *));
+ 
+-	ndev->prp_pool = malloc(MAX_PRP_POOL);
+-	if (!ndev->prp_pool) {
+-		ret = -ENOMEM;
+-		printf("Error: %s: Out of memory!\n", udev->name);
+-		goto free_nvme;
+-	}
+-	ndev->prp_entry_num = MAX_PRP_POOL >> 3;
+-
+ 	ndev->cap = nvme_readq(&ndev->bar->cap);
+ 	ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH);
+ 	ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap);
+@@ -805,6 +805,15 @@ static int nvme_probe(struct udevice *udev)
+ 	if (ret)
+ 		goto free_queue;
+ 
++	/* Allocate after the page size is known */
++	ndev->prp_pool = memalign(ndev->page_size, MAX_PRP_POOL);
++	if (!ndev->prp_pool) {
++		ret = -ENOMEM;
++		printf("Error: %s: Out of memory!\n", udev->name);
++		goto free_nvme;
++	}
++	ndev->prp_entry_num = MAX_PRP_POOL >> 3;
++
+ 	ret = nvme_setup_io_queues(ndev);
+ 	if (ret)
+ 		goto free_queue;
+-- 
+2.22.GIT
+

patches/u-boot-LSDK-19.09/0012-nvme-add-accessor-to-namespace-id-and-eui64.patch

+From 89eaac0cd956214260038ed39be675f9a3af220a Mon Sep 17 00:00:00 2001
+From: Patrick Wildt <patrick@blueri.se>
+Date: Thu, 3 Oct 2019 13:48:47 +0200
+Subject: [PATCH 3/5] nvme: add accessor to namespace id and eui64
+
+This adds a function which can be used by e.g. EFI to retrieve
+the namespace identifier and EUI64.  For that it adds the EUI64
+to its driver internal namespace structure and copies the EUI64
+during namespace identification.
+
+Signed-off-by: Patrick Wildt <patrick@blueri.se>
+Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+(cherry picked from commit c50b2883dfc1ce355dc37238741ef97cd2c5d000)
+Signed-off-by: Olof Johansson <olof@lixom.net>
+---
+ drivers/nvme/nvme.c | 13 +++++++++++++
+ drivers/nvme/nvme.h |  1 +
+ include/nvme.h      | 12 ++++++++++++
+ 3 files changed, 26 insertions(+)
+
+diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
+index 47f101e280..ee6b581d9e 100644
+--- a/drivers/nvme/nvme.c
++++ b/drivers/nvme/nvme.c
+@@ -621,6 +621,18 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev)
+ 	return 0;
+ }
+ 
++int nvme_get_namespace_id(struct udevice *udev, u32 *ns_id, u8 *eui64)
++{
++	struct nvme_ns *ns = dev_get_priv(udev);
++
++	if (ns_id)
++		*ns_id = ns->ns_id;
++	if (eui64)
++		memcpy(eui64, ns->eui64, sizeof(ns->eui64));
++
++	return 0;
++}
++
+ int nvme_scan_namespace(void)
+ {
+ 	struct uclass *uc;
+@@ -657,6 +669,7 @@ static int nvme_blk_probe(struct udevice *udev)
+ 	if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id))
+ 		return -EIO;
+ 
++	memcpy(&ns->eui64, &id->eui64, sizeof(id->eui64));
+ 	flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
+ 	ns->flbas = flbas;
+ 	ns->lba_shift = id->lbaf[flbas].ds;
+diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h
+index 922f7abfe8..0e8cb221a7 100644
+--- a/drivers/nvme/nvme.h
++++ b/drivers/nvme/nvme.h
+@@ -637,6 +637,7 @@ struct nvme_ns {
+ 	struct list_head list;
+ 	struct nvme_dev *dev;
+ 	unsigned ns_id;
++	u8 eui64[8];
+ 	int devnum;
+ 	int lba_shift;
+ 	u8 flbas;
+diff --git a/include/nvme.h b/include/nvme.h
+index 2c3d14d241..2cdf8ce320 100644
+--- a/include/nvme.h
++++ b/include/nvme.h
+@@ -78,4 +78,16 @@ int nvme_scan_namespace(void);
+  */
+ int nvme_print_info(struct udevice *udev);
+ 
++/**
++ * nvme_get_namespace_id - return namespace identifier
++ *
++ * This returns the namespace identifier.
++ *
++ * @udev:	NVMe controller device
++ * @ns_id:	Place where to put the name space identifier
++ * @eui64:	Place where to put the IEEE Extended Unique Identifier
++ * @return:	0 on success, -ve on error
++ */
++int nvme_get_namespace_id(struct udevice *udev, u32 *ns_id, u8 *eui64);
++
+ #endif /* __NVME_H__ */
+-- 
+2.22.GIT
+

patches/u-boot-LSDK-19.09/0013-nvme-flush-dcache-on-both-r-w-and-the-prp-list.patch

+From 7846531d2ad011cb2d025aac92aeefb3dffec429 Mon Sep 17 00:00:00 2001
+From: Patrick Wildt <patrick@blueri.se>
+Date: Wed, 16 Oct 2019 23:22:50 +0200
+Subject: [PATCH 4/5] nvme: flush dcache on both r/w, and the prp list
+
+It's possible that the data cache for the buffer still holds data
+to be flushed to memory, since the buffer was probably used as stack
+before.  Thus we need to make sure to flush it also on reads, since
+it's possible that the cache is automatically flused to memory after
+the NVMe DMA transfer happened, thus overwriting the NVMe transfer's
+data.  Also add a missing dcache flush for the prp list.
+
+Signed-off-by: Patrick Wildt <patrick@blueri.se>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+(cherry picked from commit 8c403402ca691c967516481b6bc2c879d683a73d)
+Signed-off-by: Olof Johansson <olof@lixom.net>
+---
+ drivers/nvme/nvme.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
+index ee6b581d9e..53ff6e89aa 100644
+--- a/drivers/nvme/nvme.c
++++ b/drivers/nvme/nvme.c
+@@ -123,6 +123,9 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
+ 	}
+ 	*prp2 = (ulong)dev->prp_pool;
+ 
++	flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
++			   dev->prp_entry_num * sizeof(u64));
++
+ 	return 0;
+ }
+ 
+@@ -705,9 +708,8 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,
+ 	u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
+ 	u64 total_lbas = blkcnt;
+ 
+-	if (!read)
+-		flush_dcache_range((unsigned long)buffer,
+-				   (unsigned long)buffer + total_len);
++	flush_dcache_range((unsigned long)buffer,
++			   (unsigned long)buffer + total_len);
+ 
+ 	c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;
+ 	c.rw.flags = 0;
+-- 
+2.22.GIT
+

patches/u-boot-LSDK-19.09/0014-nvme-use-page-aligned-buffer-for-identify-command.patch

+From 489ce106e10a3df390ea19267729e4102e88a63a Mon Sep 17 00:00:00 2001
+From: Patrick Wildt <patrick@blueri.se>
+Date: Wed, 16 Oct 2019 08:42:04 +0200
+Subject: [PATCH 5/5] nvme: use page-aligned buffer for identify command
+
+Change the stack-allocated buffer for the identification command
+to explicitly allocate page-aligned buffers.  Even though the spec
+seems to allow having admin queue commands on non page-aligned
+buffers, it seems to not be possible on my i.MX8MQ board with a
+a Silicon Power P34A80.  Since all of the NVMe drivers I have seen
+always do admin commands on a page-aligned buffer, which does work
+on my system, it makes sense for us to do that as well.
+
+Signed-off-by: Patrick Wildt <patrick@blueri.se>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+(cherry picked from commit 2f83481dff9c4f253a6ac341911d78d4984ca07b)
+Signed-off-by: Olof Johansson <olof@lixom.net>
+---
+ drivers/nvme/nvme.c | 24 ++++++++++++++++++------
+ 1 file changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
+index 53ff6e89aa..f915817aaa 100644
+--- a/drivers/nvme/nvme.c
++++ b/drivers/nvme/nvme.c
+@@ -583,14 +583,19 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
+ 
+ static int nvme_get_info_from_identify(struct nvme_dev *dev)
+ {
+-	ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl));
+-	struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf;
++	struct nvme_id_ctrl *ctrl;
+ 	int ret;
+ 	int shift = NVME_CAP_MPSMIN(dev->cap) + 12;
+ 
++	ctrl = memalign(dev->page_size, sizeof(struct nvme_id_ctrl));
++	if (!ctrl)
++		return -ENOMEM;
++
+ 	ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl);
+-	if (ret)
++	if (ret) {
++		free(ctrl);
+ 		return -EIO;
++	}
+ 
+ 	dev->nn = le32_to_cpu(ctrl->nn);
+ 	dev->vwc = ctrl->vwc;
+@@ -621,6 +626,7 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev)
+ 		dev->max_transfer_shift = 20;
+ 	}
+ 
++	free(ctrl);
+ 	return 0;
+ }
+ 
+@@ -661,16 +667,21 @@ static int nvme_blk_probe(struct udevice *udev)
+ 	struct blk_desc *desc = dev_get_uclass_platdata(udev);
+ 	struct nvme_ns *ns = dev_get_priv(udev);
+ 	u8 flbas;
+-	ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns));
+-	struct nvme_id_ns *id = (struct nvme_id_ns *)buf;
+ 	struct pci_child_platdata *pplat;
++	struct nvme_id_ns *id;
++
++	id = memalign(ndev->page_size, sizeof(struct nvme_id_ns));
++	if (!id)
++		return -ENOMEM;
+ 
+ 	memset(ns, 0, sizeof(*ns));
+ 	ns->dev = ndev;
+ 	/* extract the namespace id from the block device name */
+ 	ns->ns_id = trailing_strtol(udev->name) + 1;
+-	if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id))
++	if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id)) {
++		free(id);
+ 		return -EIO;
++	}
+ 
+ 	memcpy(&ns->eui64, &id->eui64, sizeof(id->eui64));
+ 	flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK;
+@@ -689,6 +700,7 @@ static int nvme_blk_probe(struct udevice *udev)
+ 	memcpy(desc->product, ndev->serial, sizeof(ndev->serial));
+ 	memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev));
+ 
++	free(id);
+ 	return 0;
+ }
+ 
+-- 
+2.22.GIT
+