[dev.ssa] cmd/compile: use shifted and indexed ops in SSA for ARM

This CL implements the following optimizations for ARM:
- use shifted ops (e.g. ADD R1<<2, R2) and indexed load/stores
- break up shift ops. Shifts used to be one SSA op that generates
  multiple instructions. We break them up to multiple ops, which
  allows constant folding and CSE for comparisons. Conditional moves
  are introduced for this.
- simplify zero/sign-extension ops.

Updates #15365.

Change-Id: I55e262a776a7ef2a1505d75e04d1208913c35d39
Reviewed-on: https://go-review.googlesource.com/24512
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: David Chase <drchase@google.com>

src/cmd/compile/internal/ssa/op.go

@@ -157,7 +157,13 @@ func (op Op) isTupleGenerator() bool {
 	switch op {
 	case OpAdd32carry, OpSub32carry, OpMul32uhilo,
 		OpARMADDS, OpARMSUBS, OpARMMULLU,
-		OpARMADDSconst, OpARMSUBSconst, OpARMRSBSconst:
+		OpARMADDSconst, OpARMSUBSconst, OpARMRSBSconst,
+		OpARMADDSshiftLL, OpARMSUBSshiftLL, OpARMRSBSshiftLL,
+		OpARMADDSshiftRL, OpARMSUBSshiftRL, OpARMRSBSshiftRL,
+		OpARMADDSshiftRA, OpARMSUBSshiftRA, OpARMRSBSshiftRA,
+		OpARMADDSshiftLLreg, OpARMSUBSshiftLLreg, OpARMRSBSshiftLLreg,
+		OpARMADDSshiftRLreg, OpARMSUBSshiftRLreg, OpARMRSBSshiftRLreg,
+		OpARMADDSshiftRAreg, OpARMSUBSshiftRAreg, OpARMRSBSshiftRAreg:
 		return true
 	}
 	return false