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  13. 08 Jun, 2016 2 commits
    • Cherry Zhang's avatar
      [dev.ssa] cmd/compile: fix a few bugs for SSA for ARM · fa54bf16
      Cherry Zhang authored
      - 64x signed right shift was wrong for shift larger than 0x80000000.
      - for Lsh-followed-by-Rsh, the intermediate value should be full int
        width, so when it is spilled MOVW should be used.
      - use RET for RetJmp, so the assembler can take case of restoring LR
        for non-leaf case.
      - reserve R9 in dynlink mode. R9 is used for GOT by the assembler.
      
      Progress on SSA backend for ARM. Still not complete.
      
      Updates #15365.
      
      Change-Id: I3caca256b92ff7cf96469da2feaf4868a592efc5
      Reviewed-on: https://go-review.googlesource.com/23793Reviewed-by: default avatarDavid Chase <drchase@google.com>
      fa54bf16
    • Cherry Zhang's avatar
      [dev.ssa] cmd/compile: fix scheduling of tuple ops · 225ef76c
      Cherry Zhang authored
      We want tuple-reading ops immediately follow tuple-generating op, so
      that tuple values will not be spilled/copied.
      
      The mechanism introduced in the previous CL cannot really avoid tuples
      interleaving. In this CL we always emit tuple and their selectors together.
      Maybe remove the tuple scores if it does not help on performance (todo).
      
      Also let tighten not move tuple-reading ops across blocks.
      
      In the previous CL a special case of regenerating flags with tuple-reading
      pseudo-op is added, but it did not cover end-of-block case. This is fixed
      in this CL and the condition is generalized.
      
      Progress on SSA backend for ARM. Still not complete.
      
      Updates #15365.
      
      Change-Id: I8980b34e7a64eb98153540e9e19a3782e20406ff
      Reviewed-on: https://go-review.googlesource.com/23792Reviewed-by: default avatarDavid Chase <drchase@google.com>
      225ef76c