patch_hdmi.c 126 KB
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
 *
 *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
 *
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 *  Copyright(c) 2008-2010 Intel Corporation
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 *  Copyright (c) 2006 ATI Technologies Inc.
 *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
 *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
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 *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
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 *
 *  Authors:
 *			Wu Fengguang <wfg@linux.intel.com>
 *
 *  Maintained by:
 *			Wu Fengguang <wfg@linux.intel.com>
 */

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#include <linux/init.h>
#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <sound/core.h>
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#include <sound/jack.h>
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#include <sound/asoundef.h>
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#include <sound/tlv.h>
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#include <sound/hdaudio.h>
#include <sound/hda_i915.h>
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#include <sound/hda_chmap.h>
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#include <sound/hda_codec.h>
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#include "hda_local.h"
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#include "hda_jack.h"
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#include "hda_controller.h"
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static bool static_hdmi_pcm;
module_param(static_hdmi_pcm, bool, 0644);
MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");

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static bool enable_acomp = true;
module_param(enable_acomp, bool, 0444);
MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");

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static bool enable_silent_stream =
IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
module_param(enable_silent_stream, bool, 0644);
MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");

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static bool enable_all_pins;
module_param(enable_all_pins, bool, 0444);
MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");

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struct hdmi_spec_per_cvt {
	hda_nid_t cvt_nid;
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	bool assigned;		/* the stream has been assigned */
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	bool silent_stream;	/* silent stream activated */
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	unsigned int channels_min;
	unsigned int channels_max;
	u32 rates;
	u64 formats;
	unsigned int maxbps;
};
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/* max. connections to a widget */
#define HDA_MAX_CONNECTIONS	32

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struct hdmi_spec_per_pin {
	hda_nid_t pin_nid;
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	int dev_id;
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	/* pin idx, different device entries on the same pin use the same idx */
	int pin_nid_idx;
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	int num_mux_nids;
	hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
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	int mux_idx;
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	hda_nid_t cvt_nid;
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	struct hda_codec *codec;
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	struct hdmi_eld sink_eld;
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	struct mutex lock;
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	struct delayed_work work;
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	struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
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	int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
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	int prev_pcm_idx; /* previously assigned pcm index */
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	int repoll_count;
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	bool setup; /* the stream has been set up by prepare callback */
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	bool silent_stream;
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	int channels; /* current number of channels */
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	bool non_pcm;
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	bool chmap_set;		/* channel-map override by ALSA API? */
	unsigned char chmap[8]; /* ALSA API channel-map */
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#ifdef CONFIG_SND_PROC_FS
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	struct snd_info_entry *proc_entry;
#endif
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};
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/* operations used by generic code that can be overridden by patches */
struct hdmi_ops {
	int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
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			   int dev_id, unsigned char *buf, int *eld_size);
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	void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
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				    int dev_id,
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				    int ca, int active_channels, int conn_type);

	/* enable/disable HBR (HD passthrough) */
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	int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
			     int dev_id, bool hbr);
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	int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
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			    hda_nid_t pin_nid, int dev_id, u32 stream_tag,
			    int format);
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	void (*pin_cvt_fixup)(struct hda_codec *codec,
			      struct hdmi_spec_per_pin *per_pin,
			      hda_nid_t cvt_nid);
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};

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struct hdmi_pcm {
	struct hda_pcm *pcm;
	struct snd_jack *jack;
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	struct snd_kcontrol *eld_ctl;
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};

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enum {
	SILENT_STREAM_OFF = 0,
	SILENT_STREAM_KAE,	/* use standard HDA Keep-Alive */
	SILENT_STREAM_I915,	/* Intel i915 extension */
};

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struct hdmi_spec {
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	struct hda_codec *codec;
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	int num_cvts;
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	struct snd_array cvts; /* struct hdmi_spec_per_cvt */
	hda_nid_t cvt_nids[4]; /* only for haswell fix */
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	/*
	 * num_pins is the number of virtual pins
	 * for example, there are 3 pins, and each pin
	 * has 4 device entries, then the num_pins is 12
	 */
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	int num_pins;
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	/*
	 * num_nids is the number of real pins
	 * In the above example, num_nids is 3
	 */
	int num_nids;
	/*
	 * dev_num is the number of device entries
	 * on each pin.
	 * In the above example, dev_num is 4
	 */
	int dev_num;
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	struct snd_array pins; /* struct hdmi_spec_per_pin */
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	struct hdmi_pcm pcm_rec[8];
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	struct mutex pcm_lock;
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	struct mutex bind_lock; /* for audio component binding */
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	/* pcm_bitmap means which pcms have been assigned to pins*/
	unsigned long pcm_bitmap;
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	int pcm_used;	/* counter of pcm_rec[] */
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	/* bitmap shows whether the pcm is opened in user space
	 * bit 0 means the first playback PCM (PCM3);
	 * bit 1 means the second playback PCM, and so on.
	 */
	unsigned long pcm_in_use;
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	struct hdmi_eld temp_eld;
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	struct hdmi_ops ops;
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	bool dyn_pin_out;
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	bool static_pcm_mapping;
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	/* hdmi interrupt trigger control flag for Nvidia codec */
	bool hdmi_intr_trig_ctrl;
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	bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */

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	bool intel_hsw_fixup;	/* apply Intel platform-specific fixups */
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	/*
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	 * Non-generic VIA/NVIDIA specific
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	 */
	struct hda_multi_out multiout;
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	struct hda_pcm_stream pcm_playback;
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	bool use_acomp_notifier; /* use eld_notify callback for hotplug */
	bool acomp_registered; /* audio component registered in this driver */
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	bool force_connect; /* force connectivity */
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	struct drm_audio_component_audio_ops drm_audio_ops;
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	int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
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	struct hdac_chmap chmap;
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	hda_nid_t vendor_nid;
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	const int *port_map;
	int port_num;
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	int silent_stream_type;
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};

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#ifdef CONFIG_SND_HDA_COMPONENT
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static inline bool codec_has_acomp(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
	return spec->use_acomp_notifier;
}
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#else
#define codec_has_acomp(codec)	false
#endif
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struct hdmi_audio_infoframe {
	u8 type; /* 0x84 */
	u8 ver;  /* 0x01 */
	u8 len;  /* 0x0a */

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	u8 checksum;

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	u8 CC02_CT47;	/* CC in bits 0:2, CT in 4:7 */
	u8 SS01_SF24;
	u8 CXT04;
	u8 CA;
	u8 LFEPBL01_LSV36_DM_INH7;
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};

struct dp_audio_infoframe {
	u8 type; /* 0x84 */
	u8 len;  /* 0x1b */
	u8 ver;  /* 0x11 << 2 */

	u8 CC02_CT47;	/* match with HDMI infoframe from this on */
	u8 SS01_SF24;
	u8 CXT04;
	u8 CA;
	u8 LFEPBL01_LSV36_DM_INH7;
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};

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union audio_infoframe {
	struct hdmi_audio_infoframe hdmi;
	struct dp_audio_infoframe dp;
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	DECLARE_FLEX_ARRAY(u8, bytes);
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};

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/*
 * HDMI routines
 */

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#define get_pin(spec, idx) \
	((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
#define get_cvt(spec, idx) \
	((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
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/* obtain hdmi_pcm object assigned to idx */
#define get_hdmi_pcm(spec, idx)	(&(spec)->pcm_rec[idx])
/* obtain hda_pcm object assigned to idx */
#define get_pcm_rec(spec, idx)	(get_hdmi_pcm(spec, idx)->pcm)
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static int pin_id_to_pin_index(struct hda_codec *codec,
			       hda_nid_t pin_nid, int dev_id)
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{
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	struct hdmi_spec *spec = codec->spec;
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	int pin_idx;
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	struct hdmi_spec_per_pin *per_pin;
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	/*
	 * (dev_id == -1) means it is NON-MST pin
	 * return the first virtual pin on this port
	 */
	if (dev_id == -1)
		dev_id = 0;

	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		per_pin = get_pin(spec, pin_idx);
		if ((per_pin->pin_nid == pin_nid) &&
			(per_pin->dev_id == dev_id))
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			return pin_idx;
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	}
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	codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
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	return -EINVAL;
}

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static int hinfo_to_pcm_index(struct hda_codec *codec,
			struct hda_pcm_stream *hinfo)
{
	struct hdmi_spec *spec = codec->spec;
	int pcm_idx;

	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
		if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
			return pcm_idx;

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	codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
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	return -EINVAL;
}

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static int hinfo_to_pin_index(struct hda_codec *codec,
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			      struct hda_pcm_stream *hinfo)
{
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	struct hdmi_spec *spec = codec->spec;
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	struct hdmi_spec_per_pin *per_pin;
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	int pin_idx;

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	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		per_pin = get_pin(spec, pin_idx);
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		if (per_pin->pcm &&
			per_pin->pcm->pcm->stream == hinfo)
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			return pin_idx;
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	}
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	codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
		  hinfo_to_pcm_index(codec, hinfo));
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	return -EINVAL;
}

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static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
						int pcm_idx)
{
	int i;
	struct hdmi_spec_per_pin *per_pin;

	for (i = 0; i < spec->num_pins; i++) {
		per_pin = get_pin(spec, i);
		if (per_pin->pcm_idx == pcm_idx)
			return per_pin;
	}
	return NULL;
}

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static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
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{
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	struct hdmi_spec *spec = codec->spec;
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	int cvt_idx;

	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
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		if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
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			return cvt_idx;

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	codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
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	return -EINVAL;
}

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static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
			struct snd_ctl_elem_info *uinfo)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
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	struct hdmi_spec *spec = codec->spec;
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	struct hdmi_spec_per_pin *per_pin;
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	struct hdmi_eld *eld;
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	int pcm_idx;
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	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;

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	pcm_idx = kcontrol->private_value;
	mutex_lock(&spec->pcm_lock);
	per_pin = pcm_idx_to_pin(spec, pcm_idx);
	if (!per_pin) {
		/* no pin is bound to the pcm */
		uinfo->count = 0;
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		goto unlock;
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	}
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	eld = &per_pin->sink_eld;
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	uinfo->count = eld->eld_valid ? eld->eld_size : 0;
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 unlock:
	mutex_unlock(&spec->pcm_lock);
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	return 0;
}

static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
			struct snd_ctl_elem_value *ucontrol)
{
	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
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	struct hdmi_spec *spec = codec->spec;
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	struct hdmi_spec_per_pin *per_pin;
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	struct hdmi_eld *eld;
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	int pcm_idx;
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	int err = 0;
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	pcm_idx = kcontrol->private_value;
	mutex_lock(&spec->pcm_lock);
	per_pin = pcm_idx_to_pin(spec, pcm_idx);
	if (!per_pin) {
		/* no pin is bound to the pcm */
		memset(ucontrol->value.bytes.data, 0,
		       ARRAY_SIZE(ucontrol->value.bytes.data));
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		goto unlock;
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	}
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	eld = &per_pin->sink_eld;
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	if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
	    eld->eld_size > ELD_MAX_SIZE) {
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		snd_BUG();
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		err = -EINVAL;
		goto unlock;
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	}

	memset(ucontrol->value.bytes.data, 0,
	       ARRAY_SIZE(ucontrol->value.bytes.data));
	if (eld->eld_valid)
		memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
		       eld->eld_size);
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 unlock:
	mutex_unlock(&spec->pcm_lock);
	return err;
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}

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static const struct snd_kcontrol_new eld_bytes_ctl = {
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	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
		SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
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	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
	.name = "ELD",
	.info = hdmi_eld_ctl_info,
	.get = hdmi_eld_ctl_get,
};

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static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
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			int device)
{
	struct snd_kcontrol *kctl;
	struct hdmi_spec *spec = codec->spec;
	int err;

	kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
	if (!kctl)
		return -ENOMEM;
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	kctl->private_value = pcm_idx;
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	kctl->id.device = device;

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	/* no pin nid is associated with the kctl now
	 * tbd: associate pin nid to eld ctl later
	 */
	err = snd_hda_ctl_add(codec, 0, kctl);
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	if (err < 0)
		return err;

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	get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
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	return 0;
}

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#ifdef BE_PARANOID
static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
				int *packet_index, int *byte_index)
{
	int val;

	val = snd_hda_codec_read(codec, pin_nid, 0,
				 AC_VERB_GET_HDMI_DIP_INDEX, 0);

	*packet_index = val >> 5;
	*byte_index = val & 0x1f;
}
#endif

static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
				int packet_index, int byte_index)
{
	int val;

	val = (packet_index << 5) | (byte_index & 0x1f);

	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
}

static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
				unsigned char val)
{
	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
}

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static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
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{
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	struct hdmi_spec *spec = codec->spec;
	int pin_out;

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	/* Unmute */
	if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
		snd_hda_codec_write(codec, pin_nid, 0,
				AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
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	if (spec->dyn_pin_out)
		/* Disable pin out until stream is active */
		pin_out = 0;
	else
		/* Enable pin out: some machines with GM965 gets broken output
		 * when the pin is disabled or changed while using with HDMI
		 */
		pin_out = PIN_OUT;

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	snd_hda_codec_write(codec, pin_nid, 0,
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			    AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
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}

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/*
 * ELD proc files
 */

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#ifdef CONFIG_SND_PROC_FS
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static void print_eld_info(struct snd_info_entry *entry,
			   struct snd_info_buffer *buffer)
{
	struct hdmi_spec_per_pin *per_pin = entry->private_data;

	mutex_lock(&per_pin->lock);
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	snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid,
				per_pin->dev_id, per_pin->cvt_nid);
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	mutex_unlock(&per_pin->lock);
}

static void write_eld_info(struct snd_info_entry *entry,
			   struct snd_info_buffer *buffer)
{
	struct hdmi_spec_per_pin *per_pin = entry->private_data;

	mutex_lock(&per_pin->lock);
	snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
	mutex_unlock(&per_pin->lock);
}

static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
{
	char name[32];
	struct hda_codec *codec = per_pin->codec;
	struct snd_info_entry *entry;
	int err;

	snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
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	err = snd_card_proc_new(codec->card, name, &entry);
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	if (err < 0)
		return err;

	snd_info_set_text_ops(entry, per_pin, print_eld_info);
	entry->c.text.write = write_eld_info;
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	entry->mode |= 0200;
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	per_pin->proc_entry = entry;

	return 0;
}

static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
{
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	if (!per_pin->codec->bus->shutdown) {
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		snd_info_free_entry(per_pin->proc_entry);
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		per_pin->proc_entry = NULL;
	}
}
#else
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static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
			       int index)
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{
	return 0;
}
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static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
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{
}
#endif
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/*
 * Audio InfoFrame routines
 */

/*
 * Enable Audio InfoFrame Transmission
 */
static void hdmi_start_infoframe_trans(struct hda_codec *codec,
				       hda_nid_t pin_nid)
{
	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
						AC_DIPXMIT_BEST);
}

/*
 * Disable Audio InfoFrame Transmission
 */
static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
				      hda_nid_t pin_nid)
{
	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
						AC_DIPXMIT_DISABLE);
}

static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
{
#ifdef CONFIG_SND_DEBUG_VERBOSE
	int i;
	int size;

	size = snd_hdmi_get_eld_size(codec, pin_nid);
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	codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
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	for (i = 0; i < 8; i++) {
		size = snd_hda_codec_read(codec, pin_nid, 0,
						AC_VERB_GET_HDMI_DIP_SIZE, i);
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		codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
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	}
#endif
}

static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
{
#ifdef BE_PARANOID
	int i, j;
	int size;
	int pi, bi;
	for (i = 0; i < 8; i++) {
		size = snd_hda_codec_read(codec, pin_nid, 0,
						AC_VERB_GET_HDMI_DIP_SIZE, i);
		if (size == 0)
			continue;

		hdmi_set_dip_index(codec, pin_nid, i, 0x0);
		for (j = 1; j < 1000; j++) {
			hdmi_write_dip_byte(codec, pin_nid, 0x0);
			hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
			if (pi != i)
612
				codec_dbg(codec, "dip index %d: %d != %d\n",
613 614 615 616
						bi, pi, i);
			if (bi == 0) /* byte index wrapped around */
				break;
		}
617
		codec_dbg(codec,
618 619 620 621 622 623
			"HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
			i, size, j);
	}
#endif
}

624
static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
625
{
626
	u8 *bytes = (u8 *)hdmi_ai;
627 628 629
	u8 sum = 0;
	int i;

630
	hdmi_ai->checksum = 0;
631

632
	for (i = 0; i < sizeof(*hdmi_ai); i++)
633 634
		sum += bytes[i];

635
	hdmi_ai->checksum = -sum;
636 637 638 639
}

static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
				      hda_nid_t pin_nid,
640
				      u8 *dip, int size)
641 642 643 644 645 646 647
{
	int i;

	hdmi_debug_dip_size(codec, pin_nid);
	hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */

	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
648 649
	for (i = 0; i < size; i++)
		hdmi_write_dip_byte(codec, pin_nid, dip[i]);
650 651 652
}

static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
653
				    u8 *dip, int size)
654 655 656 657
{
	u8 val;
	int i;

658
	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
659 660 661 662
	if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
							    != AC_DIPXMIT_BEST)
		return false;

663
	for (i = 0; i < size; i++) {
664 665
		val = snd_hda_codec_read(codec, pin_nid, 0,
					 AC_VERB_GET_HDMI_DIP_DATA, 0);
666
		if (val != dip[i])
667 668 669 670 671 672
			return false;
	}

	return true;
}

673 674 675 676 677 678 679 680
static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
			    int dev_id, unsigned char *buf, int *eld_size)
{
	snd_hda_set_dev_select(codec, nid, dev_id);

	return snd_hdmi_get_eld(codec, nid, buf, eld_size);
}

681
static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
682
				     hda_nid_t pin_nid, int dev_id,
683 684 685
				     int ca, int active_channels,
				     int conn_type)
{
686
	struct hdmi_spec *spec = codec->spec;
687 688
	union audio_infoframe ai;

689
	memset(&ai, 0, sizeof(ai));
690 691 692
	if ((conn_type == 0) || /* HDMI */
		/* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */
		(conn_type == 1 && spec->nv_dp_workaround)) {
693 694
		struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;

695 696 697 698 699 700 701 702 703
		if (conn_type == 0) { /* HDMI */
			hdmi_ai->type		= 0x84;
			hdmi_ai->ver		= 0x01;
			hdmi_ai->len		= 0x0a;
		} else {/* Nvidia DP */
			hdmi_ai->type		= 0x84;
			hdmi_ai->ver		= 0x1b;
			hdmi_ai->len		= 0x11 << 2;
		}
704 705 706 707 708 709 710 711 712 713 714 715
		hdmi_ai->CC02_CT47	= active_channels - 1;
		hdmi_ai->CA		= ca;
		hdmi_checksum_audio_infoframe(hdmi_ai);
	} else if (conn_type == 1) { /* DisplayPort */
		struct dp_audio_infoframe *dp_ai = &ai.dp;

		dp_ai->type		= 0x84;
		dp_ai->len		= 0x1b;
		dp_ai->ver		= 0x11 << 2;
		dp_ai->CC02_CT47	= active_channels - 1;
		dp_ai->CA		= ca;
	} else {
716
		codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
717 718 719
		return;
	}

720 721
	snd_hda_set_dev_select(codec, pin_nid, dev_id);

722 723 724 725 726 727 728
	/*
	 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
	 * sizeof(*dp_ai) to avoid partial match/update problems when
	 * the user switches between HDMI/DP monitors.
	 */
	if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
					sizeof(ai))) {
729 730
		codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
			  __func__, pin_nid, active_channels, ca);
731 732 733 734 735 736 737
		hdmi_stop_infoframe_trans(codec, pin_nid);
		hdmi_fill_audio_infoframe(codec, pin_nid,
					    ai.bytes, sizeof(ai));
		hdmi_start_infoframe_trans(codec, pin_nid);
	}
}

738 739 740
static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
				       struct hdmi_spec_per_pin *per_pin,
				       bool non_pcm)
741
{
742
	struct hdmi_spec *spec = codec->spec;
743
	struct hdac_chmap *chmap = &spec->chmap;
744
	hda_nid_t pin_nid = per_pin->pin_nid;
745
	int dev_id = per_pin->dev_id;
746
	int channels = per_pin->channels;
747
	int active_channels;
748
	struct hdmi_eld *eld;
749
	int ca;
750

751 752 753
	if (!channels)
		return;

754 755
	snd_hda_set_dev_select(codec, pin_nid, dev_id);

756 757
	/* some HW (e.g. HSW+) needs reprogramming the amp at each time */
	if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
758 759 760 761
		snd_hda_codec_write(codec, pin_nid, 0,
					    AC_VERB_SET_AMP_GAIN_MUTE,
					    AMP_OUT_UNMUTE);

762
	eld = &per_pin->sink_eld;
763

764
	ca = snd_hdac_channel_allocation(&codec->core,
765 766
			eld->info.spk_alloc, channels,
			per_pin->chmap_set, non_pcm, per_pin->chmap);
767

768
	active_channels = snd_hdac_get_active_channels(ca);
769

770 771
	chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
						active_channels);
772

773 774 775 776
	/*
	 * always configure channel mapping, it may have been changed by the
	 * user in the meantime
	 */
777
	snd_hdac_setup_channel_mapping(&spec->chmap,
778 779
				pin_nid, non_pcm, ca, channels,
				per_pin->chmap, per_pin->chmap_set);
780

781 782
	spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
				      ca, active_channels, eld->info.conn_type);
783

784
	per_pin->non_pcm = non_pcm;
785 786 787 788 789 790
}

/*
 * Unsolicited events
 */

791
static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
792

793 794
static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
				      int dev_id)
795 796
{
	struct hdmi_spec *spec = codec->spec;
797
	int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
798

799 800
	if (pin_idx < 0)
		return;
801
	mutex_lock(&spec->pcm_lock);
802
	hdmi_present_sense(get_pin(spec, pin_idx), 1);
803
	mutex_unlock(&spec->pcm_lock);
804 805
}

806 807 808
static void jack_callback(struct hda_codec *codec,
			  struct hda_jack_callback *jack)
{
809 810 811 812
	/* stop polling when notification is enabled */
	if (codec_has_acomp(codec))
		return;

813
	check_presence_and_report(codec, jack->nid, jack->dev_id);
814 815
}

816 817
static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
				 struct hda_jack_tbl *jack)
818
{
819
	jack->jack_dirty = 1;
820

821
	codec_dbg(codec,
822
		"HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
823
		codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
824
		!!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
825

826
	check_presence_and_report(codec, jack->nid, jack->dev_id);
827 828 829 830 831 832 833 834 835
}

static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
{
	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
	int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
	int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
	int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);

836
	codec_info(codec,
837
		"HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
838
		codec->addr,
839 840 841 842 843 844
		tag,
		subtag,
		cp_state,
		cp_ready);

	/* TODO */
845
	if (cp_state) {
846
		;
847 848
	}
	if (cp_ready) {
849
		;
850
	}
851 852 853 854 855 856 857
}


static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
{
	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
	int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
858
	struct hda_jack_tbl *jack;
859

860 861 862
	if (codec_has_acomp(codec))
		return;

863 864 865 866 867 868 869 870 871 872
	if (codec->dp_mst) {
		int dev_entry =
			(res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;

		jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
	} else {
		jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
	}

	if (!jack) {
873
		codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
874 875 876 877
		return;
	}

	if (subtag == 0)
878
		hdmi_intrinsic_event(codec, res, jack);
879 880 881 882
	else
		hdmi_non_intrinsic_event(codec, res);
}

883
static void haswell_verify_D0(struct hda_codec *codec,
884
		hda_nid_t cvt_nid, hda_nid_t nid)
885
{
886
	int pwr;
887

888 889 890
	/* For Haswell, the converter 1/2 may keep in D3 state after bootup,
	 * thus pins could only choose converter 0 for use. Make sure the
	 * converters are in correct power state */
891
	if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
892 893
		snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);

894
	if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
895 896 897 898 899
		snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
				    AC_PWRST_D0);
		msleep(40);
		pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
		pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
900
		codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
901 902 903
	}
}

904 905 906 907
/*
 * Callbacks
 */

908 909 910 911
/* HBR should be Non-PCM, 8 channels */
#define is_hbr_format(format) \
	((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)

912
static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
913
			      int dev_id, bool hbr)
914
{
915
	int pinctl, new_pinctl;
916

917
	if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
918
		snd_hda_set_dev_select(codec, pin_nid, dev_id);
919
		pinctl = snd_hda_codec_read(codec, pin_nid, 0,
920 921
					    AC_VERB_GET_PIN_WIDGET_CONTROL, 0);

922 923 924
		if (pinctl < 0)
			return hbr ? -EINVAL : 0;

925
		new_pinctl = pinctl & ~AC_PINCTL_EPT;
926
		if (hbr)
927 928 929 930
			new_pinctl |= AC_PINCTL_EPT_HBR;
		else
			new_pinctl |= AC_PINCTL_EPT_NATIVE;

931 932
		codec_dbg(codec,
			  "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
933
			    pin_nid,
934 935 936 937
			    pinctl == new_pinctl ? "" : "new-",
			    new_pinctl);

		if (pinctl != new_pinctl)
938
			snd_hda_codec_write(codec, pin_nid, 0,
939 940
					    AC_VERB_SET_PIN_WIDGET_CONTROL,
					    new_pinctl);
941 942
	} else if (hbr)
		return -EINVAL;
943

944 945 946 947
	return 0;
}

static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
948 949
			      hda_nid_t pin_nid, int dev_id,
			      u32 stream_tag, int format)
950 951
{
	struct hdmi_spec *spec = codec->spec;
952
	unsigned int param;
953 954
	int err;

955 956
	err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
				      is_hbr_format(format));
957 958

	if (err) {
959
		codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
960
		return err;
961
	}
962

963
	if (spec->intel_hsw_fixup) {
964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982

		/*
		 * on recent platforms IEC Coding Type is required for HBR
		 * support, read current Digital Converter settings and set
		 * ICT bitfield if needed.
		 */
		param = snd_hda_codec_read(codec, cvt_nid, 0,
					   AC_VERB_GET_DIGI_CONVERT_1, 0);

		param = (param >> 16) & ~(AC_DIG3_ICT);

		/* on recent platforms ICT mode is required for HBR support */
		if (is_hbr_format(format))
			param |= 0x1;

		snd_hda_codec_write(codec, cvt_nid, 0,
				    AC_VERB_SET_DIGI_CONVERT_3, param);
	}

983
	snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
984
	return 0;
985 986
}

987 988 989 990 991
/* Try to find an available converter
 * If pin_idx is less then zero, just try to find an available converter.
 * Otherwise, try to find an available converter and get the cvt mux index
 * of the pin.
 */
992
static int hdmi_choose_cvt(struct hda_codec *codec,
993 994
			   int pin_idx, int *cvt_id,
			   bool silent)
995 996
{
	struct hdmi_spec *spec = codec->spec;
997 998
	struct hdmi_spec_per_pin *per_pin;
	struct hdmi_spec_per_cvt *per_cvt = NULL;
999
	int cvt_idx, mux_idx = 0;
1000

1001 1002 1003 1004 1005
	/* pin_idx < 0 means no pin will be bound to the converter */
	if (pin_idx < 0)
		per_pin = NULL;
	else
		per_pin = get_pin(spec, pin_idx);
1006

1007 1008
	if (per_pin && per_pin->silent_stream) {
		cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1009 1010 1011
		per_cvt = get_cvt(spec, cvt_idx);
		if (per_cvt->assigned && !silent)
			return -EBUSY;
1012 1013 1014 1015 1016
		if (cvt_id)
			*cvt_id = cvt_idx;
		return 0;
	}

1017 1018
	/* Dynamically assign converter to stream */
	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1019
		per_cvt = get_cvt(spec, cvt_idx);
1020

1021
		/* Must not already be assigned */
1022
		if (per_cvt->assigned || per_cvt->silent_stream)
1023
			continue;
1024 1025
		if (per_pin == NULL)
			break;
1026 1027 1028 1029 1030 1031 1032 1033 1034
		/* Must be in pin's mux's list of converters */
		for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
			if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
				break;
		/* Not in mux list */
		if (mux_idx == per_pin->num_mux_nids)
			continue;
		break;
	}
1035

1036 1037
	/* No free converters */
	if (cvt_idx == spec->num_cvts)
1038
		return -EBUSY;
1039

1040 1041
	if (per_pin != NULL)
		per_pin->mux_idx = mux_idx;
1042

1043 1044 1045 1046 1047 1048
	if (cvt_id)
		*cvt_id = cvt_idx;

	return 0;
}

1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064
/* Assure the pin select the right convetor */
static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
			struct hdmi_spec_per_pin *per_pin)
{
	hda_nid_t pin_nid = per_pin->pin_nid;
	int mux_idx, curr;

	mux_idx = per_pin->mux_idx;
	curr = snd_hda_codec_read(codec, pin_nid, 0,
					  AC_VERB_GET_CONNECT_SEL, 0);
	if (curr != mux_idx)
		snd_hda_codec_write_cache(codec, pin_nid, 0,
					    AC_VERB_SET_CONNECT_SEL,
					    mux_idx);
}

1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078
/* get the mux index for the converter of the pins
 * converter's mux index is the same for all pins on Intel platform
 */
static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
			hda_nid_t cvt_nid)
{
	int i;

	for (i = 0; i < spec->num_cvts; i++)
		if (spec->cvt_nids[i] == cvt_nid)
			return i;
	return -EINVAL;
}

1079 1080 1081 1082 1083 1084 1085 1086 1087 1088
/* Intel HDMI workaround to fix audio routing issue:
 * For some Intel display codecs, pins share the same connection list.
 * So a conveter can be selected by multiple pins and playback on any of these
 * pins will generate sound on the external display, because audio flows from
 * the same converter to the display pipeline. Also muting one pin may make
 * other pins have no sound output.
 * So this function assures that an assigned converter for a pin is not selected
 * by any other pins.
 */
static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1089 1090
					 hda_nid_t pin_nid,
					 int dev_id, int mux_idx)
1091 1092
{
	struct hdmi_spec *spec = codec->spec;
1093
	hda_nid_t nid;
1094 1095
	int cvt_idx, curr;
	struct hdmi_spec_per_cvt *per_cvt;
1096 1097 1098 1099 1100 1101 1102
	struct hdmi_spec_per_pin *per_pin;
	int pin_idx;

	/* configure the pins connections */
	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		int dev_id_saved;
		int dev_num;
1103

1104 1105 1106 1107 1108 1109 1110
		per_pin = get_pin(spec, pin_idx);
		/*
		 * pin not connected to monitor
		 * no need to operate on it
		 */
		if (!per_pin->pcm)
			continue;
1111

1112 1113
		if ((per_pin->pin_nid == pin_nid) &&
			(per_pin->dev_id == dev_id))
1114
			continue;
1115

1116 1117 1118 1119 1120 1121 1122 1123
		/*
		 * if per_pin->dev_id >= dev_num,
		 * snd_hda_get_dev_select() will fail,
		 * and the following operation is unpredictable.
		 * So skip this situation.
		 */
		dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
		if (per_pin->dev_id >= dev_num)
1124 1125
			continue;

1126 1127 1128 1129 1130 1131 1132 1133 1134 1135
		nid = per_pin->pin_nid;

		/*
		 * Calling this function should not impact
		 * on the device entry selection
		 * So let's save the dev id for each pin,
		 * and restore it when return
		 */
		dev_id_saved = snd_hda_get_dev_select(codec, nid);
		snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1136
		curr = snd_hda_codec_read(codec, nid, 0,
1137
					  AC_VERB_GET_CONNECT_SEL, 0);
1138 1139
		if (curr != mux_idx) {
			snd_hda_set_dev_select(codec, nid, dev_id_saved);
1140
			continue;
1141 1142
		}

1143

1144 1145 1146 1147 1148 1149
		/* choose an unassigned converter. The conveters in the
		 * connection list are in the same order as in the codec.
		 */
		for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
			per_cvt = get_cvt(spec, cvt_idx);
			if (!per_cvt->assigned) {
1150
				codec_dbg(codec,
1151 1152
					  "choose cvt %d for pin NID 0x%x\n",
					  cvt_idx, nid);
1153
				snd_hda_codec_write_cache(codec, nid, 0,
1154
					    AC_VERB_SET_CONNECT_SEL,
1155 1156 1157
					    cvt_idx);
				break;
			}
1158
		}
1159
		snd_hda_set_dev_select(codec, nid, dev_id_saved);
1160 1161 1162
	}
}

1163 1164
/* A wrapper of intel_not_share_asigned_cvt() */
static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1165
			hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176
{
	int mux_idx;
	struct hdmi_spec *spec = codec->spec;

	/* On Intel platform, the mapping of converter nid to
	 * mux index of the pins are always the same.
	 * The pin nid may be 0, this means all pins will not
	 * share the converter.
	 */
	mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
	if (mux_idx >= 0)
1177
		intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1178 1179
}

1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190
/* skeleton caller of pin_cvt_fixup ops */
static void pin_cvt_fixup(struct hda_codec *codec,
			  struct hdmi_spec_per_pin *per_pin,
			  hda_nid_t cvt_nid)
{
	struct hdmi_spec *spec = codec->spec;

	if (spec->ops.pin_cvt_fixup)
		spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
}

1191
/* called in hdmi_pcm_open when no pin is assigned to the PCM */
1192 1193 1194 1195 1196 1197
static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
			 struct hda_codec *codec,
			 struct snd_pcm_substream *substream)
{
	struct hdmi_spec *spec = codec->spec;
	struct snd_pcm_runtime *runtime = substream->runtime;
1198
	int cvt_idx, pcm_idx;
1199 1200 1201
	struct hdmi_spec_per_cvt *per_cvt = NULL;
	int err;

1202 1203 1204 1205
	pcm_idx = hinfo_to_pcm_index(codec, hinfo);
	if (pcm_idx < 0)
		return -EINVAL;

1206
	err = hdmi_choose_cvt(codec, -1, &cvt_idx, false);
1207 1208 1209 1210
	if (err)
		return err;

	per_cvt = get_cvt(spec, cvt_idx);
1211
	per_cvt->assigned = true;
1212 1213
	hinfo->nid = per_cvt->cvt_nid;

1214
	pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1215

1216
	set_bit(pcm_idx, &spec->pcm_in_use);
1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236
	/* todo: setup spdif ctls assign */

	/* Initially set the converter's capabilities */
	hinfo->channels_min = per_cvt->channels_min;
	hinfo->channels_max = per_cvt->channels_max;
	hinfo->rates = per_cvt->rates;
	hinfo->formats = per_cvt->formats;
	hinfo->maxbps = per_cvt->maxbps;

	/* Store the updated parameters */
	runtime->hw.channels_min = hinfo->channels_min;
	runtime->hw.channels_max = hinfo->channels_max;
	runtime->hw.formats = hinfo->formats;
	runtime->hw.rates = hinfo->rates;

	snd_pcm_hw_constraint_step(substream->runtime, 0,
				   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
	return 0;
}

1237 1238 1239 1240 1241 1242 1243 1244 1245
/*
 * HDA PCM callbacks
 */
static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
			 struct hda_codec *codec,
			 struct snd_pcm_substream *substream)
{
	struct hdmi_spec *spec = codec->spec;
	struct snd_pcm_runtime *runtime = substream->runtime;
1246
	int pin_idx, cvt_idx, pcm_idx;
1247 1248 1249 1250 1251 1252
	struct hdmi_spec_per_pin *per_pin;
	struct hdmi_eld *eld;
	struct hdmi_spec_per_cvt *per_cvt = NULL;
	int err;

	/* Validate hinfo */
1253 1254
	pcm_idx = hinfo_to_pcm_index(codec, hinfo);
	if (pcm_idx < 0)
1255
		return -EINVAL;
1256

1257
	mutex_lock(&spec->pcm_lock);
1258
	pin_idx = hinfo_to_pin_index(codec, hinfo);
1259 1260 1261 1262 1263 1264
	/* no pin is assigned to the PCM
	 * PA need pcm open successfully when probe
	 */
	if (pin_idx < 0) {
		err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
		goto unlock;
1265
	}
1266

1267
	err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false);
1268 1269
	if (err < 0)
		goto unlock;
1270 1271

	per_cvt = get_cvt(spec, cvt_idx);
1272
	/* Claim converter */
1273
	per_cvt->assigned = true;
1274

1275
	set_bit(pcm_idx, &spec->pcm_in_use);
1276
	per_pin = get_pin(spec, pin_idx);
1277
	per_pin->cvt_nid = per_cvt->cvt_nid;
1278 1279
	hinfo->nid = per_cvt->cvt_nid;

1280 1281 1282 1283
	/* flip stripe flag for the assigned stream if supported */
	if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
		azx_stream(get_azx_dev(substream))->stripe = 1;

1284
	snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1285
	snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1286
			    AC_VERB_SET_CONNECT_SEL,
1287
			    per_pin->mux_idx);
1288 1289

	/* configure unused pins to choose other converters */
1290
	pin_cvt_fixup(codec, per_pin, 0);
1291

1292
	snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1293

1294
	/* Initially set the converter's capabilities */
1295 1296 1297 1298 1299
	hinfo->channels_min = per_cvt->channels_min;
	hinfo->channels_max = per_cvt->channels_max;
	hinfo->rates = per_cvt->rates;
	hinfo->formats = per_cvt->formats;
	hinfo->maxbps = per_cvt->maxbps;
1300

1301
	eld = &per_pin->sink_eld;
1302
	/* Restrict capabilities by ELD if this isn't disabled */
1303
	if (!static_hdmi_pcm && eld->eld_valid) {
1304
		snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1305
		if (hinfo->channels_min > hinfo->channels_max ||
1306
		    !hinfo->rates || !hinfo->formats) {
1307
			per_cvt->assigned = false;
1308
			hinfo->nid = 0;
1309
			snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1310 1311
			err = -ENODEV;
			goto unlock;
1312
		}
1313
	}
1314 1315

	/* Store the updated parameters */
1316 1317 1318 1319
	runtime->hw.channels_min = hinfo->channels_min;
	runtime->hw.channels_max = hinfo->channels_max;
	runtime->hw.formats = hinfo->formats;
	runtime->hw.rates = hinfo->rates;
1320 1321 1322

	snd_pcm_hw_constraint_step(substream->runtime, 0,
				   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1323 1324 1325
 unlock:
	mutex_unlock(&spec->pcm_lock);
	return err;
1326 1327
}

1328 1329 1330
/*
 * HDA/HDMI auto parsing
 */
1331
static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1332 1333
{
	struct hdmi_spec *spec = codec->spec;
1334
	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1335
	hda_nid_t pin_nid = per_pin->pin_nid;
1336
	int dev_id = per_pin->dev_id;
1337
	int conns;
1338 1339

	if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1340
		codec_warn(codec,
1341
			   "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
1342 1343 1344 1345
			   pin_nid, get_wcaps(codec, pin_nid));
		return -EINVAL;
	}

1346 1347
	snd_hda_set_dev_select(codec, pin_nid, dev_id);

1348 1349 1350 1351 1352 1353 1354 1355 1356 1357
	if (spec->intel_hsw_fixup) {
		conns = spec->num_cvts;
		memcpy(per_pin->mux_nids, spec->cvt_nids,
		       sizeof(hda_nid_t) * conns);
	} else {
		conns = snd_hda_get_raw_connections(codec, pin_nid,
						    per_pin->mux_nids,
						    HDA_MAX_CONNECTIONS);
	}

1358
	/* all the device entries on the same pin have the same conn list */
1359
	per_pin->num_mux_nids = conns;
1360 1361 1362 1363

	return 0;
}

1364
static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1365
			      struct hdmi_spec_per_pin *per_pin)
1366 1367 1368
{
	int i;

1369
	for (i = 0; i < spec->pcm_used; i++) {
1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
		if (!test_bit(i, &spec->pcm_bitmap))
			return i;
	}
	return -EBUSY;
}

static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
				struct hdmi_spec_per_pin *per_pin)
{
	int idx;

	/* pcm already be attached to the pin */
	if (per_pin->pcm)
		return;
1384 1385 1386 1387 1388 1389 1390
	/* try the previously used slot at first */
	idx = per_pin->prev_pcm_idx;
	if (idx >= 0) {
		if (!test_bit(idx, &spec->pcm_bitmap))
			goto found;
		per_pin->prev_pcm_idx = -1; /* no longer valid, clear it */
	}
1391
	idx = hdmi_find_pcm_slot(spec, per_pin);
1392
	if (idx == -EBUSY)
1393
		return;
1394
 found:
1395
	per_pin->pcm_idx = idx;
1396
	per_pin->pcm = get_hdmi_pcm(spec, idx);
1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409
	set_bit(idx, &spec->pcm_bitmap);
}

static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
				struct hdmi_spec_per_pin *per_pin)
{
	int idx;

	/* pcm already be detached from the pin */
	if (!per_pin->pcm)
		return;
	idx = per_pin->pcm_idx;
	per_pin->pcm_idx = -1;
1410
	per_pin->prev_pcm_idx = idx; /* remember the previous index */
1411 1412 1413 1414 1415
	per_pin->pcm = NULL;
	if (idx >= 0 && idx < spec->pcm_used)
		clear_bit(idx, &spec->pcm_bitmap);
}

1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
		struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
{
	int mux_idx;

	for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
		if (per_pin->mux_nids[mux_idx] == cvt_nid)
			break;
	return mux_idx;
}

static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);

static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
			   struct hdmi_spec_per_pin *per_pin)
{
	struct hda_codec *codec = per_pin->codec;
	struct hda_pcm *pcm;
	struct hda_pcm_stream *hinfo;
	struct snd_pcm_substream *substream;
	int mux_idx;
	bool non_pcm;

1439
	if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used)
1440
		return;
1441
	pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1442 1443
	if (!pcm->pcm)
		return;
1444 1445 1446 1447 1448 1449 1450 1451 1452 1453
	if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
		return;

	/* hdmi audio only uses playback and one substream */
	hinfo = pcm->stream;
	substream = pcm->pcm->streams[0].substream;

	per_pin->cvt_nid = hinfo->nid;

	mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1454 1455 1456
	if (mux_idx < per_pin->num_mux_nids) {
		snd_hda_set_dev_select(codec, per_pin->pin_nid,
				   per_pin->dev_id);
1457 1458 1459
		snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
				AC_VERB_SET_CONNECT_SEL,
				mux_idx);
1460
	}
1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484
	snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);

	non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
	if (substream->runtime)
		per_pin->channels = substream->runtime->channels;
	per_pin->setup = true;
	per_pin->mux_idx = mux_idx;

	hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
}

static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
			   struct hdmi_spec_per_pin *per_pin)
{
	if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
		snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);

	per_pin->chmap_set = false;
	memset(per_pin->chmap, 0, sizeof(per_pin->chmap));

	per_pin->setup = false;
	per_pin->channels = 0;
}

1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495
static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
					    struct hdmi_spec_per_pin *per_pin)
{
	struct hdmi_spec *spec = codec->spec;

	if (per_pin->pcm_idx >= 0)
		return spec->pcm_rec[per_pin->pcm_idx].jack;
	else
		return NULL;
}

1496 1497
/* update per_pin ELD from the given new ELD;
 * setup info frame and notification accordingly
1498
 * also notify ELD kctl and report jack status changes
1499
 */
1500
static void update_eld(struct hda_codec *codec,
1501
		       struct hdmi_spec_per_pin *per_pin,
1502 1503
		       struct hdmi_eld *eld,
		       int repoll)
1504 1505
{
	struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1506
	struct hdmi_spec *spec = codec->spec;
1507
	struct snd_jack *pcm_jack;
1508 1509
	bool old_eld_valid = pin_eld->eld_valid;
	bool eld_changed;
1510
	int pcm_idx;
1511

1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524
	if (eld->eld_valid) {
		if (eld->eld_size <= 0 ||
		    snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
				       eld->eld_size) < 0) {
			eld->eld_valid = false;
			if (repoll) {
				schedule_delayed_work(&per_pin->work,
						      msecs_to_jiffies(300));
				return;
			}
		}
	}

1525
	if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) {
1526 1527 1528 1529
		eld->eld_valid = false;
		eld->eld_size = 0;
	}

1530 1531
	/* for monitor disconnection, save pcm_idx firstly */
	pcm_idx = per_pin->pcm_idx;
1532 1533 1534 1535 1536 1537 1538

	/*
	 * pcm_idx >=0 before update_eld() means it is in monitor
	 * disconnected event. Jack must be fetched before update_eld().
	 */
	pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);

1539 1540 1541 1542 1543 1544 1545 1546
	if (!spec->static_pcm_mapping) {
		if (eld->eld_valid) {
			hdmi_attach_hda_pcm(spec, per_pin);
			hdmi_pcm_setup_pin(spec, per_pin);
		} else {
			hdmi_pcm_reset_pin(spec, per_pin);
			hdmi_detach_hda_pcm(spec, per_pin);
		}
1547
	}
1548

1549 1550 1551 1552 1553
	/* if pcm_idx == -1, it means this is in monitor connection event
	 * we can get the correct pcm_idx now.
	 */
	if (pcm_idx == -1)
		pcm_idx = per_pin->pcm_idx;
1554 1555
	if (!pcm_jack)
		pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1556

1557 1558 1559 1560
	if (eld->eld_valid)
		snd_hdmi_show_eld(codec, &eld->info);

	eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1561 1562
	eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
	if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1563 1564 1565 1566 1567
		if (pin_eld->eld_size != eld->eld_size ||
		    memcmp(pin_eld->eld_buffer, eld->eld_buffer,
			   eld->eld_size) != 0)
			eld_changed = true;

1568 1569 1570 1571 1572 1573 1574 1575 1576
	if (eld_changed) {
		pin_eld->monitor_present = eld->monitor_present;
		pin_eld->eld_valid = eld->eld_valid;
		pin_eld->eld_size = eld->eld_size;
		if (eld->eld_valid)
			memcpy(pin_eld->eld_buffer, eld->eld_buffer,
			       eld->eld_size);
		pin_eld->info = eld->info;
	}
1577 1578 1579 1580 1581 1582 1583 1584

	/*
	 * Re-setup pin and infoframe. This is needed e.g. when
	 * - sink is first plugged-in
	 * - transcoder can change during stream playback on Haswell
	 *   and this can make HW reset converter selection on a pin.
	 */
	if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1585
		pin_cvt_fixup(codec, per_pin, 0);
1586 1587 1588
		hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
	}

1589
	if (eld_changed && pcm_idx >= 0)
1590 1591 1592
		snd_ctl_notify(codec->card,
			       SNDRV_CTL_EVENT_MASK_VALUE |
			       SNDRV_CTL_EVENT_MASK_INFO,
1593
			       &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1594

1595
	if (eld_changed && pcm_jack)
1596 1597 1598
		snd_jack_report(pcm_jack,
				(eld->monitor_present && eld->eld_valid) ?
				SND_JACK_AVOUT : 0);
1599
}
1600

1601
/* update ELD and jack state via HD-audio verbs */
1602
static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1603
					 int repoll)
1604
{
1605
	struct hda_codec *codec = per_pin->codec;
1606 1607
	struct hdmi_spec *spec = codec->spec;
	struct hdmi_eld *eld = &spec->temp_eld;
1608
	struct device *dev = hda_codec_dev(codec);
1609
	hda_nid_t pin_nid = per_pin->pin_nid;
1610
	int dev_id = per_pin->dev_id;
1611 1612 1613 1614 1615 1616 1617 1618
	/*
	 * Always execute a GetPinSense verb here, even when called from
	 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
	 * response's PD bit is not the real PD value, but indicates that
	 * the real PD value changed. An older version of the HD-audio
	 * specification worked this way. Hence, we just ignore the data in
	 * the unsolicited response to avoid custom WARs.
	 */
1619
	int present;
1620 1621
	int ret;

1622 1623 1624 1625 1626
#ifdef	CONFIG_PM
	if (dev->power.runtime_status == RPM_SUSPENDING)
		return;
#endif

1627
	ret = snd_hda_power_up_pm(codec);
1628
	if (ret < 0 && pm_runtime_suspended(dev))
1629
		goto out;
1630

1631
	present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1632

1633
	mutex_lock(&per_pin->lock);
1634 1635
	eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
	if (eld->monitor_present)
1636 1637 1638
		eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
	else
		eld->eld_valid = false;
1639

1640
	codec_dbg(codec,
1641
		"HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
1642
		codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1643

1644
	if (eld->eld_valid) {
1645 1646
		if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
					  eld->eld_buffer, &eld->eld_size) < 0)
1647
			eld->eld_valid = false;
1648
	}
1649

1650
	update_eld(codec, per_pin, eld, repoll);
1651
	mutex_unlock(&per_pin->lock);
1652 1653
 out:
	snd_hda_power_down_pm(codec);
1654 1655
}

1656 1657 1658 1659 1660
#define I915_SILENT_RATE		48000
#define I915_SILENT_CHANNELS		2
#define I915_SILENT_FORMAT_BITS	16
#define I915_SILENT_FMT_MASK		0xf

1661 1662 1663 1664 1665 1666 1667 1668 1669
static void silent_stream_enable_i915(struct hda_codec *codec,
				      struct hdmi_spec_per_pin *per_pin)
{
	unsigned int format;

	snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
				 per_pin->dev_id, I915_SILENT_RATE);

	/* trigger silent stream generation in hw */
1670 1671
	format = snd_hdac_stream_format(I915_SILENT_CHANNELS, I915_SILENT_FORMAT_BITS,
					I915_SILENT_RATE);
1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699
	snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
				   I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
	usleep_range(100, 200);
	snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);

	per_pin->channels = I915_SILENT_CHANNELS;
	hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
}

static void silent_stream_set_kae(struct hda_codec *codec,
				  struct hdmi_spec_per_pin *per_pin,
				  bool enable)
{
	unsigned int param;

	codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);

	param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
	param = (param >> 16) & 0xff;

	if (enable)
		param |= AC_DIG3_KAE;
	else
		param &= ~AC_DIG3_KAE;

	snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
}

1700
static void silent_stream_enable(struct hda_codec *codec,
1701
				 struct hdmi_spec_per_pin *per_pin)
1702
{
1703 1704 1705
	struct hdmi_spec *spec = codec->spec;
	struct hdmi_spec_per_cvt *per_cvt;
	int cvt_idx, pin_idx, err;
1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719
	int keep_power = 0;

	/*
	 * Power-up will call hdmi_present_sense, so the PM calls
	 * have to be done without mutex held.
	 */

	err = snd_hda_power_up_pm(codec);
	if (err < 0 && err != -EACCES) {
		codec_err(codec,
			  "Failed to power up codec for silent stream enable ret=[%d]\n", err);
		snd_hda_power_down_pm(codec);
		return;
	}
1720 1721 1722

	mutex_lock(&per_pin->lock);

1723 1724
	if (per_pin->setup) {
		codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1725
		err = -EBUSY;
1726 1727 1728 1729
		goto unlock_out;
	}

	pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1730
	err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true);
1731 1732 1733 1734 1735 1736
	if (err) {
		codec_err(codec, "hdmi: no free converter to enable silent mode\n");
		goto unlock_out;
	}

	per_cvt = get_cvt(spec, cvt_idx);
1737
	per_cvt->silent_stream = true;
1738 1739 1740 1741 1742
	per_pin->cvt_nid = per_cvt->cvt_nid;
	per_pin->silent_stream = true;

	codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
		  per_pin->pin_nid, per_cvt->cvt_nid);
1743

1744 1745 1746 1747
	snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
	snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
				  AC_VERB_SET_CONNECT_SEL,
				  per_pin->mux_idx);
1748

1749 1750 1751
	/* configure unused pins to choose other converters */
	pin_cvt_fixup(codec, per_pin, 0);

1752 1753
	switch (spec->silent_stream_type) {
	case SILENT_STREAM_KAE:
1754
		silent_stream_enable_i915(codec, per_pin);
1755 1756 1757 1758 1759 1760 1761 1762 1763
		silent_stream_set_kae(codec, per_pin, true);
		break;
	case SILENT_STREAM_I915:
		silent_stream_enable_i915(codec, per_pin);
		keep_power = 1;
		break;
	default:
		break;
	}
1764

1765
 unlock_out:
1766
	mutex_unlock(&per_pin->lock);
1767 1768 1769

	if (err || !keep_power)
		snd_hda_power_down_pm(codec);
1770 1771
}

1772 1773 1774 1775 1776
static void silent_stream_disable(struct hda_codec *codec,
				  struct hdmi_spec_per_pin *per_pin)
{
	struct hdmi_spec *spec = codec->spec;
	struct hdmi_spec_per_cvt *per_cvt;
1777 1778 1779 1780 1781 1782 1783 1784 1785 1786
	int cvt_idx, err;

	err = snd_hda_power_up_pm(codec);
	if (err < 0 && err != -EACCES) {
		codec_err(codec,
			  "Failed to power up codec for silent stream disable ret=[%d]\n",
			  err);
		snd_hda_power_down_pm(codec);
		return;
	}
1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797

	mutex_lock(&per_pin->lock);
	if (!per_pin->silent_stream)
		goto unlock_out;

	codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
		  per_pin->pin_nid, per_pin->cvt_nid);

	cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
	if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
		per_cvt = get_cvt(spec, cvt_idx);
1798
		per_cvt->silent_stream = false;
1799 1800
	}

1801 1802 1803 1804 1805 1806 1807
	if (spec->silent_stream_type == SILENT_STREAM_I915) {
		/* release ref taken in silent_stream_enable() */
		snd_hda_power_down_pm(codec);
	} else if (spec->silent_stream_type == SILENT_STREAM_KAE) {
		silent_stream_set_kae(codec, per_pin, false);
	}

1808 1809 1810 1811
	per_pin->cvt_nid = 0;
	per_pin->silent_stream = false;

 unlock_out:
1812
	mutex_unlock(&per_pin->lock);
1813 1814

	snd_hda_power_down_pm(codec);
1815 1816
}

1817 1818 1819 1820 1821 1822
/* update ELD and jack state via audio component */
static void sync_eld_via_acomp(struct hda_codec *codec,
			       struct hdmi_spec_per_pin *per_pin)
{
	struct hdmi_spec *spec = codec->spec;
	struct hdmi_eld *eld = &spec->temp_eld;
1823
	bool monitor_prev, monitor_next;
1824

1825
	mutex_lock(&per_pin->lock);
1826
	eld->monitor_present = false;
1827
	monitor_prev = per_pin->sink_eld.monitor_present;
1828
	eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1829 1830
				      per_pin->dev_id, &eld->monitor_present,
				      eld->eld_buffer, ELD_MAX_SIZE);
1831 1832
	eld->eld_valid = (eld->eld_size > 0);
	update_eld(codec, per_pin, eld, 0);
1833
	monitor_next = per_pin->sink_eld.monitor_present;
1834
	mutex_unlock(&per_pin->lock);
1835

1836 1837
	if (spec->silent_stream_type) {
		if (!monitor_prev && monitor_next)
1838
			silent_stream_enable(codec, per_pin);
1839
		else if (monitor_prev && !monitor_next)
1840
			silent_stream_disable(codec, per_pin);
1841
	}
1842 1843
}

1844
static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1845 1846 1847
{
	struct hda_codec *codec = per_pin->codec;

1848
	if (!codec_has_acomp(codec))
1849
		hdmi_present_sense_via_verbs(per_pin, repoll);
1850
	else
1851 1852 1853
		sync_eld_via_acomp(codec, per_pin);
}

1854 1855 1856 1857
static void hdmi_repoll_eld(struct work_struct *work)
{
	struct hdmi_spec_per_pin *per_pin =
	container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1858 1859
	struct hda_codec *codec = per_pin->codec;
	struct hdmi_spec *spec = codec->spec;
1860 1861
	struct hda_jack_tbl *jack;

1862 1863
	jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
					per_pin->dev_id);
1864 1865
	if (jack)
		jack->jack_dirty = 1;
1866

1867 1868 1869
	if (per_pin->repoll_count++ > 6)
		per_pin->repoll_count = 0;

1870
	mutex_lock(&spec->pcm_lock);
1871
	hdmi_present_sense(per_pin, per_pin->repoll_count);
1872
	mutex_unlock(&spec->pcm_lock);
1873 1874
}

1875 1876 1877
static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
{
	struct hdmi_spec *spec = codec->spec;
1878 1879 1880
	unsigned int caps, config;
	int pin_idx;
	struct hdmi_spec_per_pin *per_pin;
1881
	int err;
1882
	int dev_num, i;
1883

1884
	caps = snd_hda_query_pin_caps(codec, pin_nid);
1885 1886 1887
	if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
		return 0;

1888 1889 1890 1891
	/*
	 * For DP MST audio, Configuration Default is the same for
	 * all device entries on the same pin
	 */
1892
	config = snd_hda_codec_get_pincfg(codec, pin_nid);
1893 1894
	if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
	    !spec->force_connect)
1895 1896
		return 0;

1897 1898 1899 1900
	/*
	 * To simplify the implementation, malloc all
	 * the virtual pins in the initialization statically
	 */
1901
	if (spec->intel_hsw_fixup) {
1902
		/*
1903 1904 1905 1906
		 * On Intel platforms, device entries count returned
		 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
		 * the type of receiver that is connected. Allocate pin
		 * structures based on worst case.
1907
		 */
1908
		dev_num = spec->dev_num;
1909
	} else if (codec->dp_mst) {
1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924
		dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
		/*
		 * spec->dev_num is the maxinum number of device entries
		 * among all the pins
		 */
		spec->dev_num = (spec->dev_num > dev_num) ?
			spec->dev_num : dev_num;
	} else {
		/*
		 * If the platform doesn't support DP MST,
		 * manually set dev_num to 1. This means
		 * the pin has only one device entry.
		 */
		dev_num = 1;
		spec->dev_num = 1;
1925
	}
1926

1927 1928 1929
	for (i = 0; i < dev_num; i++) {
		pin_idx = spec->num_pins;
		per_pin = snd_array_new(&spec->pins);
1930

1931 1932 1933
		if (!per_pin)
			return -ENOMEM;

1934 1935
		per_pin->pcm = NULL;
		per_pin->pcm_idx = -1;
1936
		per_pin->prev_pcm_idx = -1;
1937 1938 1939 1940 1941 1942 1943 1944
		per_pin->pin_nid = pin_nid;
		per_pin->pin_nid_idx = spec->num_nids;
		per_pin->dev_id = i;
		per_pin->non_pcm = false;
		snd_hda_set_dev_select(codec, pin_nid, i);
		err = hdmi_read_pin_conn(codec, pin_idx);
		if (err < 0)
			return err;
1945 1946
		if (!is_jack_detectable(codec, pin_nid))
			codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid);
1947 1948 1949
		spec->num_pins++;
	}
	spec->num_nids++;
1950

1951
	return 0;
1952 1953
}

1954
static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1955 1956
{
	struct hdmi_spec *spec = codec->spec;
1957 1958 1959
	struct hdmi_spec_per_cvt *per_cvt;
	unsigned int chans;
	int err;
1960

1961 1962 1963
	chans = get_wcaps(codec, cvt_nid);
	chans = get_wcaps_channels(chans);

1964 1965 1966
	per_cvt = snd_array_new(&spec->cvts);
	if (!per_cvt)
		return -ENOMEM;
1967 1968 1969

	per_cvt->cvt_nid = cvt_nid;
	per_cvt->channels_min = 2;
1970
	if (chans <= 16) {
1971
		per_cvt->channels_max = chans;
1972 1973
		if (chans > spec->chmap.channels_max)
			spec->chmap.channels_max = chans;
1974
	}
1975 1976 1977 1978

	err = snd_hda_query_supported_pcm(codec, cvt_nid,
					  &per_cvt->rates,
					  &per_cvt->formats,
1979
					  NULL,
1980 1981 1982 1983
					  &per_cvt->maxbps);
	if (err < 0)
		return err;

1984 1985 1986
	if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
		spec->cvt_nids[spec->num_cvts] = cvt_nid;
	spec->num_cvts++;
1987 1988 1989 1990

	return 0;
}

1991
static const struct snd_pci_quirk force_connect_list[] = {
1992
	SND_PCI_QUIRK(0x103c, 0x83e2, "HP EliteDesk 800 G4", 1),
1993
	SND_PCI_QUIRK(0x103c, 0x83ef, "HP MP9 G4 Retail System AMS", 1),
1994
	SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1995
	SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1996
	SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
1997
	SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1),
1998 1999
	SND_PCI_QUIRK(0x1043, 0x86ae, "ASUS", 1),  /* Z170 PRO */
	SND_PCI_QUIRK(0x1043, 0x86c7, "ASUS", 1),  /* Z170M PLUS */
2000
	SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
2001
	SND_PCI_QUIRK(0x8086, 0x2060, "Intel NUC5CPYB", 1),
2002
	SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
2003 2004 2005
	{}
};

2006 2007
static int hdmi_parse_codec(struct hda_codec *codec)
{
2008
	struct hdmi_spec *spec = codec->spec;
2009 2010
	hda_nid_t start_nid;
	unsigned int caps;
2011
	int i, nodes;
2012
	const struct snd_pci_quirk *q;
2013

2014 2015
	nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
	if (!start_nid || nodes < 0) {
2016
		codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
2017 2018 2019
		return -EINVAL;
	}

2020 2021 2022
	if (enable_all_pins)
		spec->force_connect = true;

2023 2024 2025 2026 2027
	q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);

	if (q && q->value)
		spec->force_connect = true;

2028 2029 2030 2031 2032 2033
	/*
	 * hdmi_add_pin() assumes total amount of converters to
	 * be known, so first discover all converters
	 */
	for (i = 0; i < nodes; i++) {
		hda_nid_t nid = start_nid + i;
2034

2035
		caps = get_wcaps(codec, nid);
2036 2037 2038 2039

		if (!(caps & AC_WCAP_DIGITAL))
			continue;

2040
		if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2041
			hdmi_add_cvt(codec, nid);
2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053
	}

	/* discover audio pins */
	for (i = 0; i < nodes; i++) {
		hda_nid_t nid = start_nid + i;

		caps = get_wcaps(codec, nid);

		if (!(caps & AC_WCAP_DIGITAL))
			continue;

		if (get_wcaps_type(caps) == AC_WID_PIN)
2054
			hdmi_add_pin(codec, nid);
2055 2056 2057 2058 2059
	}

	return 0;
}

2060 2061
/*
 */
2062 2063 2064 2065 2066 2067 2068
static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
{
	struct hda_spdif_out *spdif;
	bool non_pcm;

	mutex_lock(&codec->spdif_mutex);
	spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2069 2070 2071
	/* Add sanity check to pass klockwork check.
	 * This should never happen.
	 */
2072 2073
	if (WARN_ON(spdif == NULL)) {
		mutex_unlock(&codec->spdif_mutex);
2074
		return true;
2075
	}
2076 2077 2078 2079 2080
	non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
	mutex_unlock(&codec->spdif_mutex);
	return non_pcm;
}

2081 2082 2083 2084 2085 2086 2087 2088 2089 2090
/*
 * HDMI callbacks
 */

static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
					   struct hda_codec *codec,
					   unsigned int stream_tag,
					   unsigned int format,
					   struct snd_pcm_substream *substream)
{
2091 2092
	hda_nid_t cvt_nid = hinfo->nid;
	struct hdmi_spec *spec = codec->spec;
2093 2094
	int pin_idx;
	struct hdmi_spec_per_pin *per_pin;
2095
	struct snd_pcm_runtime *runtime = substream->runtime;
2096
	bool non_pcm;
2097
	int pinctl, stripe;
2098
	int err = 0;
2099

2100 2101
	mutex_lock(&spec->pcm_lock);
	pin_idx = hinfo_to_pin_index(codec, hinfo);
2102 2103 2104
	if (pin_idx < 0) {
		/* when pcm is not bound to a pin skip pin setup and return 0
		 * to make audio playback be ongoing
2105
		 */
2106
		pin_cvt_fixup(codec, NULL, cvt_nid);
2107 2108
		snd_hda_codec_setup_stream(codec, cvt_nid,
					stream_tag, 0, format);
2109
		goto unlock;
2110
	}
2111

2112
	per_pin = get_pin(spec, pin_idx);
2113 2114 2115 2116 2117 2118 2119 2120 2121 2122

	/* Verify pin:cvt selections to avoid silent audio after S3.
	 * After S3, the audio driver restores pin:cvt selections
	 * but this can happen before gfx is ready and such selection
	 * is overlooked by HW. Thus multiple pins can share a same
	 * default convertor and mute control will affect each other,
	 * which can cause a resumed audio playback become silent
	 * after S3.
	 */
	pin_cvt_fixup(codec, per_pin, 0);
2123

2124 2125
	/* Call sync_audio_rate to set the N/CTS/M manually if necessary */
	/* Todo: add DP1.2 MST audio support later */
2126
	if (codec_has_acomp(codec))
2127 2128
		snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
					 per_pin->dev_id, runtime->rate);
2129

2130
	non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2131
	mutex_lock(&per_pin->lock);
2132 2133
	per_pin->channels = substream->runtime->channels;
	per_pin->setup = true;
2134

2135 2136 2137 2138 2139 2140 2141 2142
	if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
		stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
							substream);
		snd_hda_codec_write(codec, cvt_nid, 0,
				    AC_VERB_SET_STRIPE_CONTROL,
				    stripe);
	}

2143
	hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2144
	mutex_unlock(&per_pin->lock);
2145
	if (spec->dyn_pin_out) {
2146 2147 2148
		snd_hda_set_dev_select(codec, per_pin->pin_nid,
				       per_pin->dev_id);
		pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2149
					    AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2150
		snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2151 2152 2153 2154
				    AC_VERB_SET_PIN_WIDGET_CONTROL,
				    pinctl | PIN_OUT);
	}

2155
	/* snd_hda_set_dev_select() has been called before */
2156 2157
	err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
				     per_pin->dev_id, stream_tag, format);
2158
 unlock:
2159 2160
	mutex_unlock(&spec->pcm_lock);
	return err;
2161 2162
}

2163 2164 2165 2166 2167 2168 2169 2170
static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
					     struct hda_codec *codec,
					     struct snd_pcm_substream *substream)
{
	snd_hda_codec_cleanup_stream(codec, hinfo->nid);
	return 0;
}

2171 2172 2173
static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
			  struct hda_codec *codec,
			  struct snd_pcm_substream *substream)
2174 2175
{
	struct hdmi_spec *spec = codec->spec;
2176
	int cvt_idx, pin_idx, pcm_idx;
2177 2178
	struct hdmi_spec_per_cvt *per_cvt;
	struct hdmi_spec_per_pin *per_pin;
2179
	int pinctl;
2180
	int err = 0;
2181

2182
	mutex_lock(&spec->pcm_lock);
2183
	if (hinfo->nid) {
2184
		pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2185 2186 2187 2188
		if (snd_BUG_ON(pcm_idx < 0)) {
			err = -EINVAL;
			goto unlock;
		}
2189
		cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2190 2191 2192 2193
		if (snd_BUG_ON(cvt_idx < 0)) {
			err = -EINVAL;
			goto unlock;
		}
2194
		per_cvt = get_cvt(spec, cvt_idx);
2195
		per_cvt->assigned = false;
2196 2197
		hinfo->nid = 0;

2198 2199
		azx_stream(get_azx_dev(substream))->stripe = 0;

2200
		snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2201
		clear_bit(pcm_idx, &spec->pcm_in_use);
2202
		pin_idx = hinfo_to_pin_index(codec, hinfo);
2203 2204 2205 2206
		/*
		 * In such a case, return 0 to match the behavior in
		 * hdmi_pcm_open()
		 */
2207
		if (pin_idx < 0)
2208
			goto unlock;
2209

2210
		per_pin = get_pin(spec, pin_idx);
2211

2212
		if (spec->dyn_pin_out) {
2213 2214
			snd_hda_set_dev_select(codec, per_pin->pin_nid,
					       per_pin->dev_id);
2215 2216 2217 2218 2219 2220 2221
			pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
			snd_hda_codec_write(codec, per_pin->pin_nid, 0,
					    AC_VERB_SET_PIN_WIDGET_CONTROL,
					    pinctl & ~PIN_OUT);
		}

2222
		mutex_lock(&per_pin->lock);
2223 2224
		per_pin->chmap_set = false;
		memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2225 2226 2227

		per_pin->setup = false;
		per_pin->channels = 0;
2228
		mutex_unlock(&per_pin->lock);
2229
	}
2230

2231 2232 2233
unlock:
	mutex_unlock(&spec->pcm_lock);

2234
	return err;
2235 2236 2237 2238
}

static const struct hda_pcm_ops generic_ops = {
	.open = hdmi_pcm_open,
2239
	.close = hdmi_pcm_close,
2240
	.prepare = generic_hdmi_playback_pcm_prepare,
2241
	.cleanup = generic_hdmi_playback_pcm_cleanup,
2242 2243
};

2244 2245
static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
{
2246
	struct hda_codec *codec = hdac_to_hda_codec(hdac);
2247 2248 2249 2250 2251 2252 2253 2254 2255
	struct hdmi_spec *spec = codec->spec;
	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);

	if (!per_pin)
		return 0;

	return per_pin->sink_eld.info.spk_alloc;
}

2256 2257 2258
static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
					unsigned char *chmap)
{
2259
	struct hda_codec *codec = hdac_to_hda_codec(hdac);
2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272
	struct hdmi_spec *spec = codec->spec;
	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);

	/* chmap is already set to 0 in caller */
	if (!per_pin)
		return;

	memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
}

static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
				unsigned char *chmap, int prepared)
{
2273
	struct hda_codec *codec = hdac_to_hda_codec(hdac);
2274 2275 2276
	struct hdmi_spec *spec = codec->spec;
	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);

2277 2278
	if (!per_pin)
		return;
2279 2280 2281 2282 2283 2284 2285 2286 2287 2288
	mutex_lock(&per_pin->lock);
	per_pin->chmap_set = true;
	memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
	if (prepared)
		hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
	mutex_unlock(&per_pin->lock);
}

static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
{
2289
	struct hda_codec *codec = hdac_to_hda_codec(hdac);
2290 2291 2292 2293 2294 2295
	struct hdmi_spec *spec = codec->spec;
	struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);

	return per_pin ? true:false;
}

2296 2297 2298
static int generic_hdmi_build_pcms(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
2299
	int idx, pcm_num;
2300

2301 2302
	/* limit the PCM devices to the codec converters or available PINs */
	pcm_num = min(spec->num_cvts, spec->num_pins);
2303 2304 2305
	codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);

	for (idx = 0; idx < pcm_num; idx++) {
2306
		struct hdmi_spec_per_cvt *per_cvt;
2307
		struct hda_pcm *info;
2308
		struct hda_pcm_stream *pstr;
2309

2310
		info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2311 2312
		if (!info)
			return -ENOMEM;
2313

2314
		spec->pcm_rec[idx].pcm = info;
2315
		spec->pcm_used++;
2316
		info->pcm_type = HDA_PCM_TYPE_HDMI;
2317
		info->own_chmap = true;
2318

2319
		pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2320 2321
		pstr->substreams = 1;
		pstr->ops = generic_ops;
2322 2323 2324 2325 2326

		per_cvt = get_cvt(spec, 0);
		pstr->channels_min = per_cvt->channels_min;
		pstr->channels_max = per_cvt->channels_max;

2327 2328
		/* pcm number is less than pcm_rec array size */
		if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec))
2329
			break;
2330
		/* other pstr fields are set in open */
2331 2332 2333 2334 2335
	}

	return 0;
}

2336
static void free_hdmi_jack_priv(struct snd_jack *jack)
2337
{
2338
	struct hdmi_pcm *pcm = jack->private_data;
2339

2340
	pcm->jack = NULL;
2341 2342
}

2343
static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2344
{
2345 2346
	char hdmi_str[32] = "HDMI/DP";
	struct hdmi_spec *spec = codec->spec;
2347
	struct snd_jack *jack;
2348
	int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2349 2350
	int err;

2351 2352 2353 2354
	if (pcmdev > 0)
		sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);

	err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2355 2356 2357
			   true, false);
	if (err < 0)
		return err;
2358 2359 2360 2361

	spec->pcm_rec[pcm_idx].jack = jack;
	jack->private_data = &spec->pcm_rec[pcm_idx];
	jack->private_free = free_hdmi_jack_priv;
2362 2363 2364
	return 0;
}

2365 2366 2367
static int generic_hdmi_build_controls(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
2368
	int dev, err;
2369
	int pin_idx, pcm_idx;
2370

2371
	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2372 2373 2374 2375 2376 2377
		if (!get_pcm_rec(spec, pcm_idx)->pcm) {
			/* no PCM: mark this for skipping permanently */
			set_bit(pcm_idx, &spec->pcm_bitmap);
			continue;
		}

2378
		err = generic_hdmi_build_jack(codec, pcm_idx);
2379 2380 2381
		if (err < 0)
			return err;

2382 2383 2384
		/* create the spdif for each pcm
		 * pin will be bound when monitor is connected
		 */
2385
		err = snd_hda_create_dig_out_ctls(codec,
2386 2387
					  0, spec->cvt_nids[0],
					  HDA_PCM_TYPE_HDMI);
2388 2389
		if (err < 0)
			return err;
2390
		snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2391

2392 2393 2394 2395 2396 2397 2398
		dev = get_pcm_rec(spec, pcm_idx)->device;
		if (dev != SNDRV_PCM_INVALID_DEVICE) {
			/* add control for ELD Bytes */
			err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
			if (err < 0)
				return err;
		}
2399 2400 2401 2402
	}

	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2403
		struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2404

2405 2406 2407 2408 2409
		if (spec->static_pcm_mapping) {
			hdmi_attach_hda_pcm(spec, per_pin);
			hdmi_pcm_setup_pin(spec, per_pin);
		}

2410
		pin_eld->eld_valid = false;
2411
		hdmi_present_sense(per_pin, 0);
2412 2413
	}

2414
	/* add channel maps */
2415
	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2416
		struct hda_pcm *pcm;
2417

2418
		pcm = get_pcm_rec(spec, pcm_idx);
2419
		if (!pcm || !pcm->pcm)
2420
			break;
2421
		err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2422 2423 2424 2425
		if (err < 0)
			return err;
	}

2426 2427 2428
	return 0;
}

2429
static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2430 2431
{
	struct hdmi_spec *spec = codec->spec;
2432 2433 2434
	int pin_idx;

	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2435
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2436

2437
		per_pin->codec = codec;
2438
		mutex_init(&per_pin->lock);
2439
		INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2440
		eld_proc_new(per_pin, pin_idx);
2441
	}
2442 2443 2444 2445 2446 2447 2448 2449
	return 0;
}

static int generic_hdmi_init(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
	int pin_idx;

2450
	mutex_lock(&spec->bind_lock);
2451
	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2452
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2453
		hda_nid_t pin_nid = per_pin->pin_nid;
2454
		int dev_id = per_pin->dev_id;
2455

2456
		snd_hda_set_dev_select(codec, pin_nid, dev_id);
2457
		hdmi_init_pin(codec, pin_nid);
2458 2459
		if (codec_has_acomp(codec))
			continue;
2460 2461
		snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
							jack_callback);
2462
	}
2463
	mutex_unlock(&spec->bind_lock);
2464 2465 2466
	return 0;
}

2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478
static void hdmi_array_init(struct hdmi_spec *spec, int nums)
{
	snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
	snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
}

static void hdmi_array_free(struct hdmi_spec *spec)
{
	snd_array_free(&spec->pins);
	snd_array_free(&spec->cvts);
}

2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490
static void generic_spec_free(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;

	if (spec) {
		hdmi_array_free(spec);
		kfree(spec);
		codec->spec = NULL;
	}
	codec->dp_mst = false;
}

2491 2492 2493
static void generic_hdmi_free(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
2494
	int pin_idx, pcm_idx;
2495

2496 2497 2498
	if (spec->acomp_registered) {
		snd_hdac_acomp_exit(&codec->bus->core);
	} else if (codec_has_acomp(codec)) {
2499
		snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2500
	}
2501
	codec->relaxed_resume = 0;
2502

2503
	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2504
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2505
		cancel_delayed_work_sync(&per_pin->work);
2506
		eld_proc_free(per_pin);
2507 2508 2509 2510 2511
	}

	for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
		if (spec->pcm_rec[pcm_idx].jack == NULL)
			continue;
2512
		snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack);
2513
	}
2514

2515
	generic_spec_free(codec);
2516 2517
}

2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529
static int generic_hdmi_suspend(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
	int pin_idx;

	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
		cancel_delayed_work_sync(&per_pin->work);
	}
	return 0;
}

2530 2531 2532 2533 2534
static int generic_hdmi_resume(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
	int pin_idx;

2535
	codec->patch_ops.init(codec);
2536
	snd_hda_regmap_sync(codec);
2537 2538 2539 2540 2541 2542 2543 2544

	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
		hdmi_present_sense(per_pin, 1);
	}
	return 0;
}

2545
static const struct hda_codec_ops generic_hdmi_patch_ops = {
2546 2547 2548 2549 2550
	.init			= generic_hdmi_init,
	.free			= generic_hdmi_free,
	.build_pcms		= generic_hdmi_build_pcms,
	.build_controls		= generic_hdmi_build_controls,
	.unsol_event		= hdmi_unsol_event,
2551
	.suspend		= generic_hdmi_suspend,
2552
	.resume			= generic_hdmi_resume,
2553 2554
};

2555
static const struct hdmi_ops generic_standard_hdmi_ops = {
2556
	.pin_get_eld				= hdmi_pin_get_eld,
2557 2558 2559
	.pin_setup_infoframe			= hdmi_pin_setup_infoframe,
	.pin_hbr_setup				= hdmi_pin_hbr_setup,
	.setup_stream				= hdmi_setup_stream,
2560 2561
};

2562 2563 2564 2565 2566 2567 2568 2569 2570
/* allocate codec->spec and assign/initialize generic parser ops */
static int alloc_generic_hdmi(struct hda_codec *codec)
{
	struct hdmi_spec *spec;

	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
	if (!spec)
		return -ENOMEM;

2571
	spec->codec = codec;
2572
	spec->ops = generic_standard_hdmi_ops;
2573
	spec->dev_num = 1;	/* initialize to 1 */
2574
	mutex_init(&spec->pcm_lock);
2575
	mutex_init(&spec->bind_lock);
2576 2577 2578 2579 2580
	snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);

	spec->chmap.ops.get_chmap = hdmi_get_chmap;
	spec->chmap.ops.set_chmap = hdmi_set_chmap;
	spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2581
	spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609

	codec->spec = spec;
	hdmi_array_init(spec, 4);

	codec->patch_ops = generic_hdmi_patch_ops;

	return 0;
}

/* generic HDMI parser */
static int patch_generic_hdmi(struct hda_codec *codec)
{
	int err;

	err = alloc_generic_hdmi(codec);
	if (err < 0)
		return err;

	err = hdmi_parse_codec(codec);
	if (err < 0) {
		generic_spec_free(codec);
		return err;
	}

	generic_hdmi_init_per_pins(codec);
	return 0;
}

2610 2611 2612 2613 2614 2615
/*
 * generic audio component binding
 */

/* turn on / off the unsol event jack detection dynamically */
static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2616
				  int dev_id, bool use_acomp)
2617 2618 2619
{
	struct hda_jack_tbl *tbl;

2620
	tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638
	if (tbl) {
		/* clear unsol even if component notifier is used, or re-enable
		 * if notifier is cleared
		 */
		unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
		snd_hda_codec_write_cache(codec, nid, 0,
					  AC_VERB_SET_UNSOLICITED_ENABLE, val);
	}
}

/* set up / clear component notifier dynamically */
static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
				       bool use_acomp)
{
	struct hdmi_spec *spec;
	int i;

	spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2639
	mutex_lock(&spec->bind_lock);
2640 2641
	spec->use_acomp_notifier = use_acomp;
	spec->codec->relaxed_resume = use_acomp;
2642
	spec->codec->bus->keep_power = 0;
2643
	/* reprogram each jack detection logic depending on the notifier */
2644 2645 2646 2647 2648
	for (i = 0; i < spec->num_pins; i++)
		reprogram_jack_detect(spec->codec,
				      get_pin(spec, i)->pin_nid,
				      get_pin(spec, i)->dev_id,
				      use_acomp);
2649
	mutex_unlock(&spec->bind_lock);
2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692
}

/* enable / disable the notifier via master bind / unbind */
static int generic_acomp_master_bind(struct device *dev,
				     struct drm_audio_component *acomp)
{
	generic_acomp_notifier_set(acomp, true);
	return 0;
}

static void generic_acomp_master_unbind(struct device *dev,
					struct drm_audio_component *acomp)
{
	generic_acomp_notifier_set(acomp, false);
}

/* check whether both HD-audio and DRM PCI devices belong to the same bus */
static int match_bound_vga(struct device *dev, int subtype, void *data)
{
	struct hdac_bus *bus = data;
	struct pci_dev *pci, *master;

	if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
		return 0;
	master = to_pci_dev(bus->dev);
	pci = to_pci_dev(dev);
	return master->bus == pci->bus;
}

/* audio component notifier for AMD/Nvidia HDMI codecs */
static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
{
	struct hda_codec *codec = audio_ptr;
	struct hdmi_spec *spec = codec->spec;
	hda_nid_t pin_nid = spec->port2pin(codec, port);

	if (!pin_nid)
		return;
	if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
		return;
	/* skip notification during system suspend (but not in runtime PM);
	 * the state will be updated at resume
	 */
2693
	if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723
		return;

	check_presence_and_report(codec, pin_nid, dev_id);
}

/* set up the private drm_audio_ops from the template */
static void setup_drm_audio_ops(struct hda_codec *codec,
				const struct drm_audio_component_audio_ops *ops)
{
	struct hdmi_spec *spec = codec->spec;

	spec->drm_audio_ops.audio_ptr = codec;
	/* intel_audio_codec_enable() or intel_audio_codec_disable()
	 * will call pin_eld_notify with using audio_ptr pointer
	 * We need make sure audio_ptr is really setup
	 */
	wmb();
	spec->drm_audio_ops.pin2port = ops->pin2port;
	spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
	spec->drm_audio_ops.master_bind = ops->master_bind;
	spec->drm_audio_ops.master_unbind = ops->master_unbind;
}

/* initialize the generic HDMI audio component */
static void generic_acomp_init(struct hda_codec *codec,
			       const struct drm_audio_component_audio_ops *ops,
			       int (*port2pin)(struct hda_codec *, int))
{
	struct hdmi_spec *spec = codec->spec;

2724 2725 2726 2727 2728
	if (!enable_acomp) {
		codec_info(codec, "audio component disabled by module option\n");
		return;
	}

2729 2730 2731
	spec->port2pin = port2pin;
	setup_drm_audio_ops(codec, ops);
	if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2732
				 match_bound_vga, 0)) {
2733
		spec->acomp_registered = true;
2734
	}
2735 2736
}

2737 2738 2739 2740
/*
 * Intel codec parsers and helpers
 */

2741 2742 2743 2744
#define INTEL_GET_VENDOR_VERB	0xf81
#define INTEL_SET_VENDOR_VERB	0x781
#define INTEL_EN_DP12		0x02	/* enable DP 1.2 features */
#define INTEL_EN_ALL_PIN_CVTS	0x01	/* enable 2nd & 3rd pins and convertors */
2745 2746

static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2747
					  bool update_tree)
2748 2749
{
	unsigned int vendor_param;
2750
	struct hdmi_spec *spec = codec->spec;
2751

2752
	vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2753 2754 2755 2756 2757
				INTEL_GET_VENDOR_VERB, 0);
	if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
		return;

	vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2758
	vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2759 2760 2761 2762
				INTEL_SET_VENDOR_VERB, vendor_param);
	if (vendor_param == -1)
		return;

2763 2764
	if (update_tree)
		snd_hda_codec_update_widgets(codec);
2765 2766
}

2767 2768 2769
static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
{
	unsigned int vendor_param;
2770
	struct hdmi_spec *spec = codec->spec;
2771

2772
	vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2773 2774 2775 2776 2777 2778
				INTEL_GET_VENDOR_VERB, 0);
	if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
		return;

	/* enable DP1.2 mode */
	vendor_param |= INTEL_EN_DP12;
2779
	snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2780
	snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2781 2782 2783
				INTEL_SET_VENDOR_VERB, vendor_param);
}

2784 2785 2786 2787 2788 2789 2790 2791 2792 2793
/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
 * Otherwise you may get severe h/w communication errors.
 */
static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
				unsigned int power_state)
{
	if (power_state == AC_PWRST_D0) {
		intel_haswell_enable_all_pins(codec, false);
		intel_haswell_fixup_enable_dp12(codec);
	}
2794

2795 2796 2797
	snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
	snd_hda_codec_set_power_to_all(codec, fg, power_state);
}
2798

2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823
/* There is a fixed mapping between audio pin node and display port.
 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
 *
 * on VLV, ILK:
 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
 */
static int intel_base_nid(struct hda_codec *codec)
{
	switch (codec->core.vendor_id) {
	case 0x80860054: /* ILK */
	case 0x80862804: /* ILK */
	case 0x80862882: /* VLV */
		return 4;
	default:
		return 5;
	}
}

static int intel_pin2port(void *audio_ptr, int pin_nid)
{
2824 2825 2826
	struct hda_codec *codec = audio_ptr;
	struct hdmi_spec *spec = codec->spec;
	int base_nid, i;
2827

2828 2829 2830 2831
	if (!spec->port_num) {
		base_nid = intel_base_nid(codec);
		if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
			return -1;
2832
		return pin_nid - base_nid + 1;
2833 2834 2835 2836 2837 2838 2839 2840
	}

	/*
	 * looking for the pin number in the mapping table and return
	 * the index which indicate the port number
	 */
	for (i = 0; i < spec->port_num; i++) {
		if (pin_nid == spec->port_map[i])
2841
			return i;
2842 2843
	}

2844
	codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
2845
	return -1;
2846 2847
}

2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858
static int intel_port2pin(struct hda_codec *codec, int port)
{
	struct hdmi_spec *spec = codec->spec;

	if (!spec->port_num) {
		/* we assume only from port-B to port-D */
		if (port < 1 || port > 3)
			return 0;
		return port + intel_base_nid(codec) - 1;
	}

2859
	if (port < 0 || port >= spec->port_num)
2860
		return 0;
2861
	return spec->port_map[port];
2862 2863
}

2864
static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2865 2866
{
	struct hda_codec *codec = audio_ptr;
2867
	int pin_nid;
2868
	int dev_id = pipe;
2869

2870 2871
	pin_nid = intel_port2pin(codec, port);
	if (!pin_nid)
2872
		return;
2873 2874 2875
	/* skip notification during system suspend (but not in runtime PM);
	 * the state will be updated at resume
	 */
2876
	if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2877 2878
		return;

2879
	snd_hdac_i915_set_bclk(&codec->bus->core);
2880
	check_presence_and_report(codec, pin_nid, dev_id);
2881 2882
}

2883 2884 2885 2886 2887
static const struct drm_audio_component_audio_ops intel_audio_ops = {
	.pin2port = intel_pin2port,
	.pin_eld_notify = intel_pin_eld_notify,
};

2888 2889
/* register i915 component pin_eld_notify callback */
static void register_i915_notifier(struct hda_codec *codec)
2890
{
2891
	struct hdmi_spec *spec = codec->spec;
2892

2893
	spec->use_acomp_notifier = true;
2894 2895
	spec->port2pin = intel_port2pin;
	setup_drm_audio_ops(codec, &intel_audio_ops);
2896
	snd_hdac_acomp_register_notifier(&codec->bus->core,
2897
					&spec->drm_audio_ops);
2898 2899
	/* no need for forcible resume for jack check thanks to notifier */
	codec->relaxed_resume = 1;
2900
}
2901

2902 2903
/* setup_stream ops override for HSW+ */
static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2904 2905
				 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
				 int format)
2906
{
2907 2908 2909 2910 2911 2912 2913 2914 2915 2916
	struct hdmi_spec *spec = codec->spec;
	int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id);
	struct hdmi_spec_per_pin *per_pin;
	int res;

	if (pin_idx < 0)
		per_pin = NULL;
	else
		per_pin = get_pin(spec, pin_idx);

2917
	haswell_verify_D0(codec, cvt_nid, pin_nid);
2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933

	if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
		silent_stream_set_kae(codec, per_pin, false);
		/* wait for pending transfers in codec to clear */
		usleep_range(100, 200);
	}

	res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
				stream_tag, format);

	if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
		usleep_range(100, 200);
		silent_stream_set_kae(codec, per_pin, true);
	}

	return res;
2934
}
2935

2936 2937 2938 2939 2940 2941
/* pin_cvt_fixup ops override for HSW+ and VLV+ */
static void i915_pin_cvt_fixup(struct hda_codec *codec,
			       struct hdmi_spec_per_pin *per_pin,
			       hda_nid_t cvt_nid)
{
	if (per_pin) {
2942
		haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2943 2944
		snd_hda_set_dev_select(codec, per_pin->pin_nid,
			       per_pin->dev_id);
2945 2946
		intel_verify_pin_cvt_connect(codec, per_pin);
		intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2947
				     per_pin->dev_id, per_pin->mux_idx);
2948
	} else {
2949
		intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2950 2951
	}
}
2952

2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032
static int i915_adlp_hdmi_suspend(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
	bool silent_streams = false;
	int pin_idx, res;

	res = generic_hdmi_suspend(codec);

	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);

		if (per_pin->silent_stream) {
			silent_streams = true;
			break;
		}
	}

	if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) {
		/*
		 * stream-id should remain programmed when codec goes
		 * to runtime suspend
		 */
		codec->no_stream_clean_at_suspend = 1;

		/*
		 * the system might go to S3, in which case keep-alive
		 * must be reprogrammed upon resume
		 */
		codec->forced_resume = 1;

		codec_dbg(codec, "HDMI: KAE active at suspend\n");
	} else {
		codec->no_stream_clean_at_suspend = 0;
		codec->forced_resume = 0;
	}

	return res;
}

static int i915_adlp_hdmi_resume(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
	int pin_idx, res;

	res = generic_hdmi_resume(codec);

	/* KAE not programmed at suspend, nothing to do here */
	if (!codec->no_stream_clean_at_suspend)
		return res;

	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);

		/*
		 * If system was in suspend with monitor connected,
		 * the codec setting may have been lost. Re-enable
		 * keep-alive.
		 */
		if (per_pin->silent_stream) {
			unsigned int param;

			param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
						   AC_VERB_GET_CONV, 0);
			if (!param) {
				codec_dbg(codec, "HDMI: KAE: restore stream id\n");
				silent_stream_enable_i915(codec, per_pin);
			}

			param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
						   AC_VERB_GET_DIGI_CONVERT_1, 0);
			if (!(param & (AC_DIG3_KAE << 16))) {
				codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n");
				silent_stream_set_kae(codec, per_pin, true);
			}
		}
	}

	return res;
}

3033 3034
/* precondition and allocation for Intel codecs */
static int alloc_intel_hdmi(struct hda_codec *codec)
3035
{
3036 3037
	int err;

3038
	/* requires i915 binding */
3039 3040
	if (!codec->bus->core.audio_component) {
		codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
3041 3042
		/* set probe_id here to prevent generic fallback binding */
		codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
3043
		return -ENODEV;
3044
	}
3045

3046 3047 3048 3049 3050 3051
	err = alloc_generic_hdmi(codec);
	if (err < 0)
		return err;
	/* no need to handle unsol events */
	codec->patch_ops.unsol_event = NULL;
	return 0;
3052 3053 3054 3055 3056
}

/* parse and post-process for Intel codecs */
static int parse_intel_hdmi(struct hda_codec *codec)
{
3057 3058 3059 3060 3061
	int err, retries = 3;

	do {
		err = hdmi_parse_codec(codec);
	} while (err < 0 && retries--);
3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073

	if (err < 0) {
		generic_spec_free(codec);
		return err;
	}

	generic_hdmi_init_per_pins(codec);
	register_i915_notifier(codec);
	return 0;
}

/* Intel Haswell and onwards; audio component with eld notifier */
3074
static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
3075 3076
				 const int *port_map, int port_num, int dev_num,
				 bool send_silent_stream)
3077 3078 3079 3080 3081
{
	struct hdmi_spec *spec;
	int err;

	err = alloc_intel_hdmi(codec);
3082 3083 3084
	if (err < 0)
		return err;
	spec = codec->spec;
3085
	codec->dp_mst = true;
3086
	spec->vendor_nid = vendor_nid;
3087 3088
	spec->port_map = port_map;
	spec->port_num = port_num;
3089
	spec->intel_hsw_fixup = true;
3090
	spec->dev_num = dev_num;
3091

3092 3093 3094
	intel_haswell_enable_all_pins(codec, true);
	intel_haswell_fixup_enable_dp12(codec);

3095
	codec->display_power_control = 1;
3096

3097 3098 3099 3100
	codec->patch_ops.set_power_state = haswell_set_power_state;
	codec->depop_delay = 0;
	codec->auto_runtime_pm = 1;

3101
	spec->ops.setup_stream = i915_hsw_setup_stream;
3102
	spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3103

3104 3105 3106 3107
	/*
	 * Enable silent stream feature, if it is enabled via
	 * module param or Kconfig option
	 */
3108
	if (send_silent_stream)
3109
		spec->silent_stream_type = SILENT_STREAM_I915;
3110

3111
	return parse_intel_hdmi(codec);
3112 3113
}

3114 3115
static int patch_i915_hsw_hdmi(struct hda_codec *codec)
{
3116 3117
	return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
				     enable_silent_stream);
3118 3119 3120 3121
}

static int patch_i915_glk_hdmi(struct hda_codec *codec)
{
3122 3123 3124 3125 3126 3127
	/*
	 * Silent stream calls audio component .get_power() from
	 * .pin_eld_notify(). On GLK this will deadlock in i915 due
	 * to the audio vs. CDCLK workaround.
	 */
	return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
3128 3129 3130 3131 3132 3133
}

static int patch_i915_icl_hdmi(struct hda_codec *codec)
{
	/*
	 * pin to port mapping table where the value indicate the pin number and
3134
	 * the index indicate the port number.
3135
	 */
3136
	static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3137

3138 3139
	return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
				     enable_silent_stream);
3140 3141
}

3142 3143 3144 3145
static int patch_i915_tgl_hdmi(struct hda_codec *codec)
{
	/*
	 * pin to port mapping table where the value indicate the pin number and
3146
	 * the index indicate the port number.
3147 3148
	 */
	static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3149

3150 3151
	return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
				     enable_silent_stream);
3152 3153
}

3154 3155 3156 3157 3158 3159 3160 3161 3162
static int patch_i915_adlp_hdmi(struct hda_codec *codec)
{
	struct hdmi_spec *spec;
	int res;

	res = patch_i915_tgl_hdmi(codec);
	if (!res) {
		spec = codec->spec;

3163
		if (spec->silent_stream_type) {
3164
			spec->silent_stream_type = SILENT_STREAM_KAE;
3165 3166 3167 3168

			codec->patch_ops.resume = i915_adlp_hdmi_resume;
			codec->patch_ops.suspend = i915_adlp_hdmi_suspend;
		}
3169 3170 3171 3172 3173
	}

	return res;
}

3174
/* Intel Baytrail and Braswell; with eld notifier */
3175 3176 3177 3178 3179
static int patch_i915_byt_hdmi(struct hda_codec *codec)
{
	struct hdmi_spec *spec;
	int err;

3180
	err = alloc_intel_hdmi(codec);
3181 3182 3183
	if (err < 0)
		return err;
	spec = codec->spec;
3184

3185 3186 3187
	/* For Valleyview/Cherryview, only the display codec is in the display
	 * power well and can use link_power ops to request/release the power.
	 */
3188
	codec->display_power_control = 1;
3189

3190 3191
	codec->depop_delay = 0;
	codec->auto_runtime_pm = 1;
3192

3193 3194
	spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;

3195
	return parse_intel_hdmi(codec);
3196 3197
}

3198
/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3199 3200 3201 3202
static int patch_i915_cpt_hdmi(struct hda_codec *codec)
{
	int err;

3203
	err = alloc_intel_hdmi(codec);
3204 3205
	if (err < 0)
		return err;
3206
	return parse_intel_hdmi(codec);
3207 3208
}

3209 3210 3211 3212 3213 3214 3215
/*
 * Shared non-generic implementations
 */

static int simple_playback_build_pcms(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
3216
	struct hda_pcm *info;
3217 3218
	unsigned int chans;
	struct hda_pcm_stream *pstr;
3219
	struct hdmi_spec_per_cvt *per_cvt;
3220

3221 3222
	per_cvt = get_cvt(spec, 0);
	chans = get_wcaps(codec, per_cvt->cvt_nid);
3223
	chans = get_wcaps_channels(chans);
3224

3225
	info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3226 3227
	if (!info)
		return -ENOMEM;
3228
	spec->pcm_rec[0].pcm = info;
3229 3230 3231
	info->pcm_type = HDA_PCM_TYPE_HDMI;
	pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
	*pstr = spec->pcm_playback;
3232
	pstr->nid = per_cvt->cvt_nid;
3233 3234
	if (pstr->channels_max <= 2 && chans && chans <= 16)
		pstr->channels_max = chans;
3235 3236 3237 3238

	return 0;
}

3239 3240 3241 3242
/* unsolicited event for jack sensing */
static void simple_hdmi_unsol_event(struct hda_codec *codec,
				    unsigned int res)
{
3243
	snd_hda_jack_set_dirty_all(codec);
3244 3245 3246 3247 3248 3249 3250 3251
	snd_hda_jack_report_sync(codec);
}

/* generic_hdmi_build_jack can be used for simple_hdmi, too,
 * as long as spec->pins[] is set correctly
 */
#define simple_hdmi_build_jack	generic_hdmi_build_jack

3252 3253 3254
static int simple_playback_build_controls(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
3255
	struct hdmi_spec_per_cvt *per_cvt;
3256 3257
	int err;

3258
	per_cvt = get_cvt(spec, 0);
3259 3260 3261
	err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
					  per_cvt->cvt_nid,
					  HDA_PCM_TYPE_HDMI);
3262 3263 3264
	if (err < 0)
		return err;
	return simple_hdmi_build_jack(codec, 0);
3265 3266
}

3267 3268 3269
static int simple_playback_init(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
3270 3271
	struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
	hda_nid_t pin = per_pin->pin_nid;
3272 3273 3274 3275 3276 3277 3278

	snd_hda_codec_write(codec, pin, 0,
			    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
	/* some codecs require to unmute the pin */
	if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
		snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
				    AMP_OUT_UNMUTE);
3279
	snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3280 3281 3282
	return 0;
}

3283 3284 3285 3286
static void simple_playback_free(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;

3287
	hdmi_array_free(spec);
3288 3289 3290
	kfree(spec);
}

3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302
/*
 * Nvidia specific implementations
 */

#define Nv_VERB_SET_Channel_Allocation          0xF79
#define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
#define Nv_VERB_SET_Audio_Protection_On         0xF98
#define Nv_VERB_SET_Audio_Protection_Off        0xF99

#define nvhdmi_master_con_nid_7x	0x04
#define nvhdmi_master_pin_nid_7x	0x05

3303
static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3304 3305 3306 3307
	/*front, rear, clfe, rear_surr */
	0x6, 0x8, 0xa, 0xc,
};

3308 3309 3310 3311 3312 3313 3314 3315 3316
static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
	/* set audio protect on */
	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
	/* enable digital output on pin widget */
	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
	{} /* terminator */
};

static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343
	/* set audio protect on */
	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
	/* enable digital output on pin widget */
	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
	{ 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
	{ 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
	{ 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
	{ 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
	{} /* terminator */
};

#ifdef LIMITED_RATE_FMT_SUPPORT
/* support only the safe format and rate */
#define SUPPORTED_RATES		SNDRV_PCM_RATE_48000
#define SUPPORTED_MAXBPS	16
#define SUPPORTED_FORMATS	SNDRV_PCM_FMTBIT_S16_LE
#else
/* support all rates and formats */
#define SUPPORTED_RATES \
	(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
	SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
	 SNDRV_PCM_RATE_192000)
#define SUPPORTED_MAXBPS	24
#define SUPPORTED_FORMATS \
	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
#endif

3344 3345 3346 3347 3348 3349 3350
static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
{
	snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
	return 0;
}

static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3351
{
3352
	snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3353 3354 3355
	return 0;
}

3356
static const unsigned int channels_2_6_8[] = {
3357 3358 3359
	2, 6, 8
};

3360
static const unsigned int channels_2_8[] = {
3361 3362 3363
	2, 8
};

3364
static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3365 3366 3367 3368 3369
	.count = ARRAY_SIZE(channels_2_6_8),
	.list = channels_2_6_8,
	.mask = 0,
};

3370
static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3371 3372 3373 3374 3375
	.count = ARRAY_SIZE(channels_2_8),
	.list = channels_2_8,
	.mask = 0,
};

3376 3377 3378 3379 3380
static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
				    struct hda_codec *codec,
				    struct snd_pcm_substream *substream)
{
	struct hdmi_spec *spec = codec->spec;
3381
	const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3382

3383
	switch (codec->preset->vendor_id) {
3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400
	case 0x10de0002:
	case 0x10de0003:
	case 0x10de0005:
	case 0x10de0006:
		hw_constraints_channels = &hw_constraints_2_8_channels;
		break;
	case 0x10de0007:
		hw_constraints_channels = &hw_constraints_2_6_8_channels;
		break;
	default:
		break;
	}

	if (hw_constraints_channels != NULL) {
		snd_pcm_hw_constraint_list(substream->runtime, 0,
				SNDRV_PCM_HW_PARAM_CHANNELS,
				hw_constraints_channels);
3401 3402 3403
	} else {
		snd_pcm_hw_constraint_step(substream->runtime, 0,
					   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3404 3405
	}

3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427
	return snd_hda_multi_out_dig_open(codec, &spec->multiout);
}

static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
				     struct hda_codec *codec,
				     struct snd_pcm_substream *substream)
{
	struct hdmi_spec *spec = codec->spec;
	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
}

static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
				       struct hda_codec *codec,
				       unsigned int stream_tag,
				       unsigned int format,
				       struct snd_pcm_substream *substream)
{
	struct hdmi_spec *spec = codec->spec;
	return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
					     stream_tag, format, substream);
}

3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443
static const struct hda_pcm_stream simple_pcm_playback = {
	.substreams = 1,
	.channels_min = 2,
	.channels_max = 2,
	.ops = {
		.open = simple_playback_pcm_open,
		.close = simple_playback_pcm_close,
		.prepare = simple_playback_pcm_prepare
	},
};

static const struct hda_codec_ops simple_hdmi_patch_ops = {
	.build_controls = simple_playback_build_controls,
	.build_pcms = simple_playback_build_pcms,
	.init = simple_playback_init,
	.free = simple_playback_free,
3444
	.unsol_event = simple_hdmi_unsol_event,
3445 3446 3447 3448 3449 3450
};

static int patch_simple_hdmi(struct hda_codec *codec,
			     hda_nid_t cvt_nid, hda_nid_t pin_nid)
{
	struct hdmi_spec *spec;
3451 3452
	struct hdmi_spec_per_cvt *per_cvt;
	struct hdmi_spec_per_pin *per_pin;
3453 3454 3455 3456 3457

	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
	if (!spec)
		return -ENOMEM;

3458
	spec->codec = codec;
3459
	codec->spec = spec;
3460
	hdmi_array_init(spec, 1);
3461 3462 3463 3464 3465 3466

	spec->multiout.num_dacs = 0;  /* no analog */
	spec->multiout.max_channels = 2;
	spec->multiout.dig_out_nid = cvt_nid;
	spec->num_cvts = 1;
	spec->num_pins = 1;
3467 3468 3469 3470 3471 3472 3473 3474
	per_pin = snd_array_new(&spec->pins);
	per_cvt = snd_array_new(&spec->cvts);
	if (!per_pin || !per_cvt) {
		simple_playback_free(codec);
		return -ENOMEM;
	}
	per_cvt->cvt_nid = cvt_nid;
	per_pin->pin_nid = pin_nid;
3475 3476 3477 3478 3479 3480 3481
	spec->pcm_playback = simple_pcm_playback;

	codec->patch_ops = simple_hdmi_patch_ops;

	return 0;
}

3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514
static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
						    int channels)
{
	unsigned int chanmask;
	int chan = channels ? (channels - 1) : 1;

	switch (channels) {
	default:
	case 0:
	case 2:
		chanmask = 0x00;
		break;
	case 4:
		chanmask = 0x08;
		break;
	case 6:
		chanmask = 0x0b;
		break;
	case 8:
		chanmask = 0x13;
		break;
	}

	/* Set the audio infoframe channel allocation and checksum fields.  The
	 * channel count is computed implicitly by the hardware. */
	snd_hda_codec_write(codec, 0x1, 0,
			Nv_VERB_SET_Channel_Allocation, chanmask);

	snd_hda_codec_write(codec, 0x1, 0,
			Nv_VERB_SET_Info_Frame_Checksum,
			(0x71 - chan - chanmask));
}

3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532
static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
				   struct hda_codec *codec,
				   struct snd_pcm_substream *substream)
{
	struct hdmi_spec *spec = codec->spec;
	int i;

	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
			0, AC_VERB_SET_CHANNEL_STREAMID, 0);
	for (i = 0; i < 4; i++) {
		/* set the stream id */
		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
				AC_VERB_SET_CHANNEL_STREAMID, 0);
		/* set the stream format */
		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
				AC_VERB_SET_STREAM_FORMAT, 0);
	}

3533 3534 3535 3536
	/* The audio hardware sends a channel count of 0x7 (8ch) when all the
	 * streams are disabled. */
	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);

3537 3538 3539 3540 3541 3542 3543 3544 3545 3546
	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
}

static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
				     struct hda_codec *codec,
				     unsigned int stream_tag,
				     unsigned int format,
				     struct snd_pcm_substream *substream)
{
	int chs;
3547
	unsigned int dataDCC2, channel_id;
3548
	int i;
3549
	struct hdmi_spec *spec = codec->spec;
3550
	struct hda_spdif_out *spdif;
3551
	struct hdmi_spec_per_cvt *per_cvt;
3552 3553

	mutex_lock(&codec->spdif_mutex);
3554 3555
	per_cvt = get_cvt(spec, 0);
	spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3556 3557 3558 3559 3560 3561

	chs = substream->runtime->channels;

	dataDCC2 = 0x2;

	/* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3562
	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3563 3564 3565 3566
		snd_hda_codec_write(codec,
				nvhdmi_master_con_nid_7x,
				0,
				AC_VERB_SET_DIGI_CONVERT_1,
3567
				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578

	/* set the stream id */
	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
			AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);

	/* set the stream format */
	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
			AC_VERB_SET_STREAM_FORMAT, format);

	/* turn on again (if needed) */
	/* enable and set the channel status audio/data flag */
3579
	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3580 3581 3582 3583
		snd_hda_codec_write(codec,
				nvhdmi_master_con_nid_7x,
				0,
				AC_VERB_SET_DIGI_CONVERT_1,
3584
				spdif->ctls & 0xff);
3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600
		snd_hda_codec_write(codec,
				nvhdmi_master_con_nid_7x,
				0,
				AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
	}

	for (i = 0; i < 4; i++) {
		if (chs == 2)
			channel_id = 0;
		else
			channel_id = i * 2;

		/* turn off SPDIF once;
		 *otherwise the IEC958 bits won't be updated
		 */
		if (codec->spdif_status_reset &&
3601
		(spdif->ctls & AC_DIG1_ENABLE))
3602 3603 3604 3605
			snd_hda_codec_write(codec,
				nvhdmi_con_nids_7x[i],
				0,
				AC_VERB_SET_DIGI_CONVERT_1,
3606
				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621
		/* set the stream id */
		snd_hda_codec_write(codec,
				nvhdmi_con_nids_7x[i],
				0,
				AC_VERB_SET_CHANNEL_STREAMID,
				(stream_tag << 4) | channel_id);
		/* set the stream format */
		snd_hda_codec_write(codec,
				nvhdmi_con_nids_7x[i],
				0,
				AC_VERB_SET_STREAM_FORMAT,
				format);
		/* turn on again (if needed) */
		/* enable and set the channel status audio/data flag */
		if (codec->spdif_status_reset &&
3622
		(spdif->ctls & AC_DIG1_ENABLE)) {
3623 3624 3625 3626
			snd_hda_codec_write(codec,
					nvhdmi_con_nids_7x[i],
					0,
					AC_VERB_SET_DIGI_CONVERT_1,
3627
					spdif->ctls & 0xff);
3628 3629 3630 3631 3632 3633 3634
			snd_hda_codec_write(codec,
					nvhdmi_con_nids_7x[i],
					0,
					AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
		}
	}

3635
	nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3636 3637 3638 3639 3640

	mutex_unlock(&codec->spdif_mutex);
	return 0;
}

3641
static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658
	.substreams = 1,
	.channels_min = 2,
	.channels_max = 8,
	.nid = nvhdmi_master_con_nid_7x,
	.rates = SUPPORTED_RATES,
	.maxbps = SUPPORTED_MAXBPS,
	.formats = SUPPORTED_FORMATS,
	.ops = {
		.open = simple_playback_pcm_open,
		.close = nvhdmi_8ch_7x_pcm_close,
		.prepare = nvhdmi_8ch_7x_pcm_prepare
	},
};

static int patch_nvhdmi_2ch(struct hda_codec *codec)
{
	struct hdmi_spec *spec;
3659 3660 3661 3662
	int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
				    nvhdmi_master_pin_nid_7x);
	if (err < 0)
		return err;
3663

3664
	codec->patch_ops.init = nvhdmi_7x_init_2ch;
3665 3666 3667 3668 3669
	/* override the PCM rates, etc, as the codec doesn't give full list */
	spec = codec->spec;
	spec->pcm_playback.rates = SUPPORTED_RATES;
	spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
	spec->pcm_playback.formats = SUPPORTED_FORMATS;
3670
	spec->nv_dp_workaround = true;
3671 3672 3673
	return 0;
}

3674 3675 3676 3677
static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
	int err = simple_playback_build_pcms(codec);
3678 3679 3680 3681
	if (!err) {
		struct hda_pcm *info = get_pcm_rec(spec, 0);
		info->own_chmap = true;
	}
3682 3683 3684 3685 3686 3687
	return err;
}

static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
{
	struct hdmi_spec *spec = codec->spec;
3688
	struct hda_pcm *info;
3689 3690 3691 3692 3693 3694 3695 3696
	struct snd_pcm_chmap *chmap;
	int err;

	err = simple_playback_build_controls(codec);
	if (err < 0)
		return err;

	/* add channel maps */
3697 3698
	info = get_pcm_rec(spec, 0);
	err = snd_pcm_add_chmap_ctls(info->pcm,
3699 3700 3701 3702
				     SNDRV_PCM_STREAM_PLAYBACK,
				     snd_pcm_alt_chmaps, 8, 0, &chmap);
	if (err < 0)
		return err;
3703
	switch (codec->preset->vendor_id) {
3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715
	case 0x10de0002:
	case 0x10de0003:
	case 0x10de0005:
	case 0x10de0006:
		chmap->channel_mask = (1U << 2) | (1U << 8);
		break;
	case 0x10de0007:
		chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
	}
	return 0;
}

3716 3717 3718 3719 3720 3721 3722 3723
static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
{
	struct hdmi_spec *spec;
	int err = patch_nvhdmi_2ch(codec);
	if (err < 0)
		return err;
	spec = codec->spec;
	spec->multiout.max_channels = 8;
3724
	spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3725
	codec->patch_ops.init = nvhdmi_7x_init_8ch;
3726 3727
	codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
	codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3728 3729 3730 3731 3732

	/* Initialize the audio infoframe channel mask and checksum to something
	 * valid */
	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);

3733 3734 3735
	return 0;
}

3736 3737 3738 3739 3740
/*
 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
 * - 0x10de0015
 * - 0x10de0040
 */
3741
static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3742
		struct hdac_cea_channel_speaker_allocation *cap, int channels)
3743 3744 3745 3746
{
	if (cap->ca_index == 0x00 && channels == 2)
		return SNDRV_CTL_TLVT_CHMAP_FIXED;

3747 3748 3749 3750 3751 3752
	/* If the speaker allocation matches the channel count, it is OK. */
	if (cap->channels != channels)
		return -1;

	/* all channels are remappable freely */
	return SNDRV_CTL_TLVT_CHMAP_VAR;
3753 3754
}

3755 3756
static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
		int ca, int chs, unsigned char *map)
3757 3758 3759 3760 3761 3762 3763
{
	if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
		return -EINVAL;

	return 0;
}

3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783
/* map from pin NID to port; port is 0-based */
/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
{
	return pin_nid - 4;
}

/* reverse-map from port to pin NID: see above */
static int nvhdmi_port2pin(struct hda_codec *codec, int port)
{
	return port + 4;
}

static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
	.pin2port = nvhdmi_pin2port,
	.pin_eld_notify = generic_acomp_pin_eld_notify,
	.master_bind = generic_acomp_master_bind,
	.master_unbind = generic_acomp_master_unbind,
};

3784 3785 3786 3787 3788
static int patch_nvhdmi(struct hda_codec *codec)
{
	struct hdmi_spec *spec;
	int err;

3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808
	err = alloc_generic_hdmi(codec);
	if (err < 0)
		return err;
	codec->dp_mst = true;

	spec = codec->spec;

	err = hdmi_parse_codec(codec);
	if (err < 0) {
		generic_spec_free(codec);
		return err;
	}

	generic_hdmi_init_per_pins(codec);

	spec->dyn_pin_out = true;

	spec->chmap.ops.chmap_cea_alloc_validate_get_type =
		nvhdmi_chmap_cea_alloc_validate_get_type;
	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3809
	spec->nv_dp_workaround = true;
3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822

	codec->link_down_at_suspend = 1;

	generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);

	return 0;
}

static int patch_nvhdmi_legacy(struct hda_codec *codec)
{
	struct hdmi_spec *spec;
	int err;

3823 3824 3825 3826 3827
	err = patch_generic_hdmi(codec);
	if (err)
		return err;

	spec = codec->spec;
3828
	spec->dyn_pin_out = true;
3829

3830
	spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3831
		nvhdmi_chmap_cea_alloc_validate_get_type;
3832
	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3833
	spec->nv_dp_workaround = true;
3834

3835 3836
	codec->link_down_at_suspend = 1;

3837 3838 3839
	return 0;
}

3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861
/*
 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
 * accessed using vendor-defined verbs. These registers can be used for
 * interoperability between the HDA and HDMI drivers.
 */

/* Audio Function Group node */
#define NVIDIA_AFG_NID 0x01

/*
 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
 * additional bit (at position 30) to signal the validity of the format.
 *
 * | 31      | 30    | 29  16 | 15   0 |
 * +---------+-------+--------+--------+
 * | TRIGGER | VALID | UNUSED | FORMAT |
 * +-----------------------------------|
 *
 * Note that for the trigger bit to take effect it needs to change value
3862 3863 3864
 * (i.e. it needs to be toggled). The trigger bit is not applicable from
 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt
 * trigger to hdmi.
3865
 */
3866
#define NVIDIA_SET_HOST_INTR		0xf80
3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884
#define NVIDIA_GET_SCRATCH0		0xfa6
#define NVIDIA_SET_SCRATCH0_BYTE0	0xfa7
#define NVIDIA_SET_SCRATCH0_BYTE1	0xfa8
#define NVIDIA_SET_SCRATCH0_BYTE2	0xfa9
#define NVIDIA_SET_SCRATCH0_BYTE3	0xfaa
#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
#define NVIDIA_SCRATCH_VALID   (1 << 6)

#define NVIDIA_GET_SCRATCH1		0xfab
#define NVIDIA_SET_SCRATCH1_BYTE0	0xfac
#define NVIDIA_SET_SCRATCH1_BYTE1	0xfad
#define NVIDIA_SET_SCRATCH1_BYTE2	0xfae
#define NVIDIA_SET_SCRATCH1_BYTE3	0xfaf

/*
 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
 * the format is invalidated so that the HDMI codec can be disabled.
 */
3885 3886 3887
static void tegra_hdmi_set_format(struct hda_codec *codec,
				  hda_nid_t cvt_nid,
				  unsigned int format)
3888 3889
{
	unsigned int value;
3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900
	unsigned int nid = NVIDIA_AFG_NID;
	struct hdmi_spec *spec = codec->spec;

	/*
	 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.
	 * This resulted in moving scratch registers from audio function
	 * group to converter widget context. So CVT NID should be used for
	 * scratch register read/write for DP MST supported Tegra HDA codec.
	 */
	if (codec->dp_mst)
		nid = cvt_nid;
3901 3902

	/* bits [31:30] contain the trigger and valid bits */
3903
	value = snd_hda_codec_read(codec, nid, 0,
3904 3905 3906 3907
				   NVIDIA_GET_SCRATCH0, 0);
	value = (value >> 24) & 0xff;

	/* bits [15:0] are used to store the HDA format */
3908
	snd_hda_codec_write(codec, nid, 0,
3909 3910
			    NVIDIA_SET_SCRATCH0_BYTE0,
			    (format >> 0) & 0xff);
3911
	snd_hda_codec_write(codec, nid, 0,
3912 3913 3914 3915
			    NVIDIA_SET_SCRATCH0_BYTE1,
			    (format >> 8) & 0xff);

	/* bits [16:24] are unused */
3916
	snd_hda_codec_write(codec, nid, 0,
3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927
			    NVIDIA_SET_SCRATCH0_BYTE2, 0);

	/*
	 * Bit 30 signals that the data is valid and hence that HDMI audio can
	 * be enabled.
	 */
	if (format == 0)
		value &= ~NVIDIA_SCRATCH_VALID;
	else
		value |= NVIDIA_SCRATCH_VALID;

3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945
	if (spec->hdmi_intr_trig_ctrl) {
		/*
		 * For Tegra HDA Codec design from TEGRA234 onwards, the
		 * Interrupt to hdmi driver is triggered by writing
		 * non-zero values to verb 0xF80 instead of 31st bit of
		 * scratch register.
		 */
		snd_hda_codec_write(codec, nid, 0,
				NVIDIA_SET_SCRATCH0_BYTE3, value);
		snd_hda_codec_write(codec, nid, 0,
				NVIDIA_SET_HOST_INTR, 0x1);
	} else {
		/*
		 * Whenever the 31st trigger bit is toggled, an interrupt is raised
		 * in the HDMI codec. The HDMI driver will use that as trigger
		 * to update its configuration.
		 */
		value ^= NVIDIA_SCRATCH_TRIGGER;
3946

3947 3948 3949
		snd_hda_codec_write(codec, nid, 0,
				NVIDIA_SET_SCRATCH0_BYTE3, value);
	}
3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965
}

static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
				  struct hda_codec *codec,
				  unsigned int stream_tag,
				  unsigned int format,
				  struct snd_pcm_substream *substream)
{
	int err;

	err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
						format, substream);
	if (err < 0)
		return err;

	/* notify the HDMI codec of the format change */
3966
	tegra_hdmi_set_format(codec, hinfo->nid, format);
3967 3968 3969 3970 3971 3972 3973 3974 3975

	return 0;
}

static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
				  struct hda_codec *codec,
				  struct snd_pcm_substream *substream)
{
	/* invalidate the format in the HDMI codec */
3976
	tegra_hdmi_set_format(codec, hinfo->nid, 0);
3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020

	return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
}

static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
{
	struct hdmi_spec *spec = codec->spec;
	unsigned int i;

	for (i = 0; i < spec->num_pins; i++) {
		struct hda_pcm *pcm = get_pcm_rec(spec, i);

		if (pcm->pcm_type == type)
			return pcm;
	}

	return NULL;
}

static int tegra_hdmi_build_pcms(struct hda_codec *codec)
{
	struct hda_pcm_stream *stream;
	struct hda_pcm *pcm;
	int err;

	err = generic_hdmi_build_pcms(codec);
	if (err < 0)
		return err;

	pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
	if (!pcm)
		return -ENODEV;

	/*
	 * Override ->prepare() and ->cleanup() operations to notify the HDMI
	 * codec about format changes.
	 */
	stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
	stream->ops.prepare = tegra_hdmi_pcm_prepare;
	stream->ops.cleanup = tegra_hdmi_pcm_cleanup;

	return 0;
}

4021
static int tegra_hdmi_init(struct hda_codec *codec)
4022
{
4023 4024
	struct hdmi_spec *spec = codec->spec;
	int i, err;
4025

4026 4027 4028
	err = hdmi_parse_codec(codec);
	if (err < 0) {
		generic_spec_free(codec);
4029
		return err;
4030 4031 4032 4033 4034 4035 4036 4037
	}

	for (i = 0; i < spec->num_cvts; i++)
		snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
					AC_VERB_SET_DIGI_CONVERT_1,
					AC_DIG1_ENABLE);

	generic_hdmi_init_per_pins(codec);
4038

4039
	codec->depop_delay = 10;
4040
	codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
4041 4042 4043 4044
	spec->chmap.ops.chmap_cea_alloc_validate_get_type =
		nvhdmi_chmap_cea_alloc_validate_get_type;
	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;

4045 4046 4047
	spec->chmap.ops.chmap_cea_alloc_validate_get_type =
		nvhdmi_chmap_cea_alloc_validate_get_type;
	spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4048
	spec->nv_dp_workaround = true;
4049 4050 4051 4052

	return 0;
}

4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075
static int patch_tegra_hdmi(struct hda_codec *codec)
{
	int err;

	err = alloc_generic_hdmi(codec);
	if (err < 0)
		return err;

	return tegra_hdmi_init(codec);
}

static int patch_tegra234_hdmi(struct hda_codec *codec)
{
	struct hdmi_spec *spec;
	int err;

	err = alloc_generic_hdmi(codec);
	if (err < 0)
		return err;

	codec->dp_mst = true;
	spec = codec->spec;
	spec->dyn_pin_out = true;
4076
	spec->hdmi_intr_trig_ctrl = true;
4077 4078 4079 4080

	return tegra_hdmi_init(codec);
}

4081
/*
4082
 * ATI/AMD-specific implementations
4083 4084
 */

4085
#define is_amdhdmi_rev3_or_later(codec) \
4086 4087
	((codec)->core.vendor_id == 0x1002aa01 && \
	 ((codec)->core.revision_id & 0xff00) >= 0x0300)
4088 4089 4090 4091 4092 4093 4094 4095 4096
#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)

/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
#define ATI_VERB_SET_CHANNEL_ALLOCATION	0x771
#define ATI_VERB_SET_DOWNMIX_INFO	0x772
#define ATI_VERB_SET_MULTICHANNEL_01	0x777
#define ATI_VERB_SET_MULTICHANNEL_23	0x778
#define ATI_VERB_SET_MULTICHANNEL_45	0x779
#define ATI_VERB_SET_MULTICHANNEL_67	0x77a
4097
#define ATI_VERB_SET_HBR_CONTROL	0x77c
4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108
#define ATI_VERB_SET_MULTICHANNEL_1	0x785
#define ATI_VERB_SET_MULTICHANNEL_3	0x786
#define ATI_VERB_SET_MULTICHANNEL_5	0x787
#define ATI_VERB_SET_MULTICHANNEL_7	0x788
#define ATI_VERB_SET_MULTICHANNEL_MODE	0x789
#define ATI_VERB_GET_CHANNEL_ALLOCATION	0xf71
#define ATI_VERB_GET_DOWNMIX_INFO	0xf72
#define ATI_VERB_GET_MULTICHANNEL_01	0xf77
#define ATI_VERB_GET_MULTICHANNEL_23	0xf78
#define ATI_VERB_GET_MULTICHANNEL_45	0xf79
#define ATI_VERB_GET_MULTICHANNEL_67	0xf7a
4109
#define ATI_VERB_GET_HBR_CONTROL	0xf7c
4110 4111 4112 4113 4114 4115
#define ATI_VERB_GET_MULTICHANNEL_1	0xf85
#define ATI_VERB_GET_MULTICHANNEL_3	0xf86
#define ATI_VERB_GET_MULTICHANNEL_5	0xf87
#define ATI_VERB_GET_MULTICHANNEL_7	0xf88
#define ATI_VERB_GET_MULTICHANNEL_MODE	0xf89

4116 4117 4118 4119
/* AMD specific HDA cvt verbs */
#define ATI_VERB_SET_RAMP_RATE		0x770
#define ATI_VERB_GET_RAMP_RATE		0xf70

4120 4121 4122 4123 4124
#define ATI_OUT_ENABLE 0x1

#define ATI_MULTICHANNEL_MODE_PAIRED	0
#define ATI_MULTICHANNEL_MODE_SINGLE	1

4125 4126 4127
#define ATI_HBR_CAPABLE 0x01
#define ATI_HBR_ENABLE 0x10

4128
static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
4129
			       int dev_id, unsigned char *buf, int *eld_size)
4130
{
4131
	WARN_ON(dev_id != 0);
4132 4133 4134 4135 4136
	/* call hda_eld.c ATI/AMD-specific function */
	return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
				    is_amdhdmi_rev3_or_later(codec));
}

4137 4138
static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
					hda_nid_t pin_nid, int dev_id, int ca,
4139 4140
					int active_channels, int conn_type)
{
4141
	WARN_ON(dev_id != 0);
4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161
	snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
}

static int atihdmi_paired_swap_fc_lfe(int pos)
{
	/*
	 * ATI/AMD have automatic FC/LFE swap built-in
	 * when in pairwise mapping mode.
	 */

	switch (pos) {
		/* see channel_allocations[].speakers[] */
		case 2: return 3;
		case 3: return 2;
		default: break;
	}

	return pos;
}

4162 4163
static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
			int ca, int chs, unsigned char *map)
4164
{
4165
	struct hdac_cea_channel_speaker_allocation *cap;
4166 4167 4168 4169
	int i, j;

	/* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */

4170
	cap = snd_hdac_get_ch_alloc_from_ca(ca);
4171
	for (i = 0; i < chs; ++i) {
4172
		int mask = snd_hdac_chmap_to_spk_mask(map[i]);
4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187
		bool ok = false;
		bool companion_ok = false;

		if (!mask)
			continue;

		for (j = 0 + i % 2; j < 8; j += 2) {
			int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
			if (cap->speakers[chan_idx] == mask) {
				/* channel is in a supported position */
				ok = true;

				if (i % 2 == 0 && i + 1 < chs) {
					/* even channel, check the odd companion */
					int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
4188
					int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209
					int comp_mask_act = cap->speakers[comp_chan_idx];

					if (comp_mask_req == comp_mask_act)
						companion_ok = true;
					else
						return -EINVAL;
				}
				break;
			}
		}

		if (!ok)
			return -EINVAL;

		if (companion_ok)
			i++; /* companion channel already checked */
	}

	return 0;
}

4210 4211
static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
		hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4212
{
4213
	struct hda_codec *codec = hdac_to_hda_codec(hdac);
4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245
	int verb;
	int ati_channel_setup = 0;

	if (hdmi_slot > 7)
		return -EINVAL;

	if (!has_amd_full_remap_support(codec)) {
		hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);

		/* In case this is an odd slot but without stream channel, do not
		 * disable the slot since the corresponding even slot could have a
		 * channel. In case neither have a channel, the slot pair will be
		 * disabled when this function is called for the even slot. */
		if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
			return 0;

		hdmi_slot -= hdmi_slot % 2;

		if (stream_channel != 0xf)
			stream_channel -= stream_channel % 2;
	}

	verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;

	/* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */

	if (stream_channel != 0xf)
		ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;

	return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
}

4246 4247
static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
				hda_nid_t pin_nid, int asp_slot)
4248
{
4249
	struct hda_codec *codec = hdac_to_hda_codec(hdac);
4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274
	bool was_odd = false;
	int ati_asp_slot = asp_slot;
	int verb;
	int ati_channel_setup;

	if (asp_slot > 7)
		return -EINVAL;

	if (!has_amd_full_remap_support(codec)) {
		ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
		if (ati_asp_slot % 2 != 0) {
			ati_asp_slot -= 1;
			was_odd = true;
		}
	}

	verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;

	ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);

	if (!(ati_channel_setup & ATI_OUT_ENABLE))
		return 0xf;

	return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
}
4275

4276 4277
static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
		struct hdac_chmap *chmap,
4278
		struct hdac_cea_channel_speaker_allocation *cap,
4279
		int channels)
4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305
{
	int c;

	/*
	 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
	 * we need to take that into account (a single channel may take 2
	 * channel slots if we need to carry a silent channel next to it).
	 * On Rev3+ AMD codecs this function is not used.
	 */
	int chanpairs = 0;

	/* We only produce even-numbered channel count TLVs */
	if ((channels % 2) != 0)
		return -1;

	for (c = 0; c < 7; c += 2) {
		if (cap->speakers[c] || cap->speakers[c+1])
			chanpairs++;
	}

	if (chanpairs * 2 != channels)
		return -1;

	return SNDRV_CTL_TLVT_CHMAP_PAIRED;
}

4306
static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4307 4308
		struct hdac_cea_channel_speaker_allocation *cap,
		unsigned int *chmap, int channels)
4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324
{
	/* produce paired maps for pre-rev3 ATI/AMD codecs */
	int count = 0;
	int c;

	for (c = 7; c >= 0; c--) {
		int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
		int spk = cap->speakers[chan];
		if (!spk) {
			/* add N/A channel if the companion channel is occupied */
			if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
				chmap[count++] = SNDRV_CHMAP_NA;

			continue;
		}

4325
		chmap[count++] = snd_hdac_spk_to_chmap(spk);
4326 4327 4328 4329 4330
	}

	WARN_ON(count != channels);
}

4331
static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4332
				 int dev_id, bool hbr)
4333 4334 4335
{
	int hbr_ctl, hbr_ctl_new;

4336 4337
	WARN_ON(dev_id != 0);

4338
	hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4339
	if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4340 4341 4342 4343 4344
		if (hbr)
			hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
		else
			hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;

4345 4346
		codec_dbg(codec,
			  "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361
				pin_nid,
				hbr_ctl == hbr_ctl_new ? "" : "new-",
				hbr_ctl_new);

		if (hbr_ctl != hbr_ctl_new)
			snd_hda_codec_write(codec, pin_nid, 0,
						ATI_VERB_SET_HBR_CONTROL,
						hbr_ctl_new);

	} else if (hbr)
		return -EINVAL;

	return 0;
}

4362
static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4363 4364
				hda_nid_t pin_nid, int dev_id,
				u32 stream_tag, int format)
4365 4366 4367 4368 4369 4370 4371 4372 4373 4374
{
	if (is_amdhdmi_rev3_or_later(codec)) {
		int ramp_rate = 180; /* default as per AMD spec */
		/* disable ramp-up/down for non-pcm as per AMD spec */
		if (format & AC_FMT_TYPE_NON_PCM)
			ramp_rate = 0;

		snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
	}

4375 4376
	return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
				 stream_tag, format);
4377 4378 4379
}


4380
static int atihdmi_init(struct hda_codec *codec)
4381 4382
{
	struct hdmi_spec *spec = codec->spec;
4383
	int pin_idx, err;
4384

4385 4386 4387
	err = generic_hdmi_init(codec);

	if (err)
4388
		return err;
4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400

	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);

		/* make sure downmix information in infoframe is zero */
		snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);

		/* enable channel-wise remap mode if supported */
		if (has_amd_full_remap_support(codec))
			snd_hda_codec_write(codec, per_pin->pin_nid, 0,
					    ATI_VERB_SET_MULTICHANNEL_MODE,
					    ATI_MULTICHANNEL_MODE_SINGLE);
4401
	}
4402
	codec->auto_runtime_pm = 1;
4403

4404 4405 4406
	return 0;
}

4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426
/* map from pin NID to port; port is 0-based */
/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
{
	return pin_nid / 2 - 1;
}

/* reverse-map from port to pin NID: see above */
static int atihdmi_port2pin(struct hda_codec *codec, int port)
{
	return port * 2 + 3;
}

static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
	.pin2port = atihdmi_pin2port,
	.pin_eld_notify = generic_acomp_pin_eld_notify,
	.master_bind = generic_acomp_master_bind,
	.master_unbind = generic_acomp_master_unbind,
};

4427 4428 4429
static int patch_atihdmi(struct hda_codec *codec)
{
	struct hdmi_spec *spec;
4430 4431 4432 4433 4434 4435
	struct hdmi_spec_per_cvt *per_cvt;
	int err, cvt_idx;

	err = patch_generic_hdmi(codec);

	if (err)
4436
		return err;
4437 4438 4439

	codec->patch_ops.init = atihdmi_init;

4440
	spec = codec->spec;
4441

4442 4443
	spec->static_pcm_mapping = true;

4444
	spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4445
	spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4446
	spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4447
	spec->ops.setup_stream = atihdmi_setup_stream;
4448

4449 4450 4451
	spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
	spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;

4452 4453
	if (!has_amd_full_remap_support(codec)) {
		/* override to ATI/AMD-specific versions with pairwise mapping */
4454
		spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4455
			atihdmi_paired_chmap_cea_alloc_validate_get_type;
4456 4457 4458
		spec->chmap.ops.cea_alloc_to_tlv_chmap =
				atihdmi_paired_cea_alloc_to_tlv_chmap;
		spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469
	}

	/* ATI/AMD converters do not advertise all of their capabilities */
	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
		per_cvt = get_cvt(spec, cvt_idx);
		per_cvt->channels_max = max(per_cvt->channels_max, 8u);
		per_cvt->rates |= SUPPORTED_RATES;
		per_cvt->formats |= SUPPORTED_FORMATS;
		per_cvt->maxbps = max(per_cvt->maxbps, 24u);
	}

4470
	spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4471

4472 4473 4474 4475 4476
	/* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
	 * the link-down as is.  Tell the core to allow it.
	 */
	codec->link_down_at_suspend = 1;

4477 4478
	generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);

4479 4480 4481
	return 0;
}

4482 4483 4484 4485 4486 4487
/* VIA HDMI Implementation */
#define VIAHDMI_CVT_NID	0x02	/* audio converter1 */
#define VIAHDMI_PIN_NID	0x03	/* HDMI output pin1 */

static int patch_via_hdmi(struct hda_codec *codec)
{
4488
	return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4489
}
4490

4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506
static int patch_gf_hdmi(struct hda_codec *codec)
{
	int err;

	err = patch_generic_hdmi(codec);
	if (err)
		return err;

	/*
	 * Glenfly GPUs have two codecs, stream switches from one codec to
	 * another, need to do actual clean-ups in codec_cleanup_stream
	 */
	codec->no_sticky_stream = 1;
	return 0;
}

4507 4508 4509
/*
 * patch entries
 */
4510
static const struct hda_device_id snd_hda_id_hdmi[] = {
4511
HDA_CODEC_ENTRY(0x00147a47, "Loongson HDMI",	patch_generic_hdmi),
4512 4513 4514 4515 4516 4517 4518
HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",	patch_atihdmi),
HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",	patch_atihdmi),
HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",	patch_atihdmi),
HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",	patch_atihdmi),
HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",	patch_generic_hdmi),
HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",	patch_generic_hdmi),
HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",	patch_generic_hdmi),
4519
HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI",	patch_nvhdmi_2ch),
4520 4521
HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
4522
HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI",	patch_nvhdmi_8ch_7x),
4523 4524 4525
HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",	patch_nvhdmi_8ch_7x),
HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",	patch_nvhdmi_8ch_7x),
4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538
HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",	patch_nvhdmi_legacy),
4539
/* 17 is known to be absent */
4540 4541 4542 4543 4544
HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",	patch_nvhdmi_legacy),
HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",	patch_nvhdmi_legacy),
4545 4546 4547 4548
HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",	patch_tegra_hdmi),
HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",	patch_tegra_hdmi),
HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",	patch_tegra_hdmi),
HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP",	patch_tegra_hdmi),
4549 4550 4551 4552
HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4553
HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
4554 4555 4556 4557 4558
HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",	patch_nvhdmi),
4559 4560
HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP",	patch_nvhdmi),
4561
HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",	patch_nvhdmi),
4562
HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP",	patch_nvhdmi),
4563
HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",	patch_nvhdmi),
4564 4565
HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP",	patch_nvhdmi),
4566 4567 4568 4569
HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",	patch_nvhdmi_2ch),
HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",	patch_nvhdmi),
4570 4571 4572 4573 4574
HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP",	patch_nvhdmi),
4575
HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",	patch_nvhdmi),
4576
HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP",	patch_nvhdmi),
4577
HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP",	patch_nvhdmi),
4578
HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP",	patch_nvhdmi),
4579
HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP",	patch_nvhdmi),
4580
HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP",	patch_nvhdmi),
4581 4582 4583 4584 4585 4586 4587 4588 4589 4590
HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP",	patch_nvhdmi),
4591 4592 4593 4594 4595
HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP",	patch_nvhdmi),
4596 4597 4598 4599 4600
HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP",	patch_nvhdmi),
HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP",	patch_nvhdmi),
4601
HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",	patch_nvhdmi_2ch),
4602
HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI",	patch_nvhdmi_2ch),
4603 4604 4605 4606 4607 4608
HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP",	patch_gf_hdmi),
HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP",	patch_gf_hdmi),
HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP",	patch_gf_hdmi),
HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP",	patch_gf_hdmi),
HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP",	patch_gf_hdmi),
HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP",	patch_gf_hdmi),
4609 4610 4611 4612
HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",	patch_via_hdmi),
HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",	patch_via_hdmi),
HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",	patch_generic_hdmi),
HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",	patch_generic_hdmi),
4613
HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",	patch_i915_cpt_hdmi),
4614
HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI",	patch_i915_glk_hdmi),
4615 4616 4617
HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",	patch_generic_hdmi),
HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",	patch_generic_hdmi),
HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",	patch_generic_hdmi),
4618
HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",	patch_i915_cpt_hdmi),
4619 4620
HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI",	patch_i915_cpt_hdmi),
HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4621 4622 4623 4624 4625
HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",	patch_i915_hsw_hdmi),
HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",	patch_i915_hsw_hdmi),
HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",	patch_i915_hsw_hdmi),
HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",	patch_i915_hsw_hdmi),
HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI",	patch_i915_hsw_hdmi),
4626
HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI",	patch_i915_glk_hdmi),
4627
HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI",	patch_i915_glk_hdmi),
4628
HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI",	patch_i915_icl_hdmi),
4629
HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI",	patch_i915_tgl_hdmi),
4630
HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI",	patch_i915_tgl_hdmi),
4631
HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI",	patch_i915_tgl_hdmi),
4632
HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI",	patch_i915_tgl_hdmi),
4633
HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI",	patch_i915_tgl_hdmi),
4634
HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI",	patch_i915_tgl_hdmi),
4635
HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI",	patch_i915_icl_hdmi),
4636
HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI",	patch_i915_icl_hdmi),
4637
HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
4638
HDA_CODEC_ENTRY(0x8086281d, "Meteor Lake HDMI",	patch_i915_adlp_hdmi),
4639
HDA_CODEC_ENTRY(0x8086281e, "Battlemage HDMI",	patch_i915_adlp_hdmi),
4640
HDA_CODEC_ENTRY(0x8086281f, "Raptor Lake P HDMI",	patch_i915_adlp_hdmi),
4641
HDA_CODEC_ENTRY(0x80862820, "Lunar Lake HDMI",	patch_i915_adlp_hdmi),
4642
HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",	patch_generic_hdmi),
4643 4644
HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI",	patch_i915_byt_hdmi),
HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",	patch_i915_byt_hdmi),
4645
HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",	patch_generic_hdmi),
4646
/* special ID for generic HDMI */
4647
HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4648 4649
{} /* terminator */
};
4650
MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4651 4652 4653 4654 4655 4656 4657

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("HDMI HD-audio codec");
MODULE_ALIAS("snd-hda-codec-intelhdmi");
MODULE_ALIAS("snd-hda-codec-nvhdmi");
MODULE_ALIAS("snd-hda-codec-atihdmi");

4658
static struct hda_codec_driver hdmi_driver = {
4659
	.id = snd_hda_id_hdmi,
4660 4661
};

4662
module_hda_codec_driver(hdmi_driver);