sama5d3.dtsi 43.3 KB
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
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 *                applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
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 *
 *  Copyright (C) 2013 Atmel,
 *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
 */

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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/at91.h>
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/ {
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	#address-cells = <1>;
	#size-cells = <1>;
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	model = "Atmel SAMA5D3 family SoC";
	compatible = "atmel,sama5d3", "atmel,sama5";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		serial1 = &usart0;
		serial2 = &usart1;
		serial3 = &usart2;
		serial4 = &usart3;
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		serial5 = &uart0;
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		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		gpio4 = &pioE;
		tcb0 = &tcb0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		ssc0 = &ssc0;
		ssc1 = &ssc1;
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		pwm0 = &pwm0;
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	};
	cpus {
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		#address-cells = <1>;
		#size-cells = <0>;
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		cpu@0 {
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			device_type = "cpu";
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			compatible = "arm,cortex-a5";
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			reg = <0x0>;
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		};
	};

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	pmu {
		compatible = "arm,cortex-a5-pmu";
		interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
	};

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	memory {
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		device_type = "memory";
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		reg = <0x20000000 0x8000000>;
	};

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	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
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		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
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		adc_op_clk: adc_op_clk{
			compatible = "fixed-clock";
			#clock-cells = <0>;
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			clock-frequency = <1000000>;
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		};
	};

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	sram: sram@300000 {
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		compatible = "mmio-sram";
		reg = <0x00300000 0x20000>;
	};

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	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			mmc0: mmc@f0000000 {
				compatible = "atmel,hsmci";
				reg = <0xf0000000 0x600>;
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				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
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				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
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				dma-names = "rxtx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
				status = "disabled";
				#address-cells = <1>;
				#size-cells = <0>;
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				clocks = <&mci0_clk>;
				clock-names = "mci_clk";
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			};

			spi0: spi@f0004000 {
				#address-cells = <1>;
				#size-cells = <0>;
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				compatible = "atmel,at91rm9200-spi";
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				reg = <0xf0004000 0x100>;
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				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
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				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
				       <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0>;
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				clocks = <&spi0_clk>;
				clock-names = "spi_clk";
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				status = "disabled";
			};

			ssc0: ssc@f0008000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf0008000 0x4000>;
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				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
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				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
				       <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
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				clocks = <&ssc0_clk>;
				clock-names = "pclk";
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				status = "disabled";
			};

			tcb0: timer@f0010000 {
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				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
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				reg = <0xf0010000 0x100>;
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				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
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				clocks = <&tcb0_clk>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
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			};

			i2c0: i2c@f0014000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf0014000 0x4000>;
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				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
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				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
				       <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
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				dma-names = "tx", "rx";
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				pinctrl-names = "default", "gpio";
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				pinctrl-0 = <&pinctrl_i2c0>;
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				pinctrl-1 = <&pinctrl_i2c0_gpio>;
				sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>;
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				#address-cells = <1>;
				#size-cells = <0>;
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				clocks = <&twi0_clk>;
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				status = "disabled";
			};

			i2c1: i2c@f0018000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf0018000 0x4000>;
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				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
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				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
				       <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
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				dma-names = "tx", "rx";
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				pinctrl-names = "default", "gpio";
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				pinctrl-0 = <&pinctrl_i2c1>;
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				pinctrl-1 = <&pinctrl_i2c1_gpio>;
				sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioC 27 GPIO_ACTIVE_HIGH>;
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				#address-cells = <1>;
				#size-cells = <0>;
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				clocks = <&twi1_clk>;
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				status = "disabled";
			};

			usart0: serial@f001c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf001c000 0x100>;
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				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
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				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
				       <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart0>;
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				clocks = <&usart0_clk>;
				clock-names = "usart";
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				status = "disabled";
			};

			usart1: serial@f0020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf0020000 0x100>;
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				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
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				dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
				       <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart1>;
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				clocks = <&usart1_clk>;
				clock-names = "usart";
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				status = "disabled";
			};

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			uart0: serial@f0024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf0024000 0x100>;
				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart0>;
				clocks = <&uart0_clk>;
				clock-names = "usart";
				status = "disabled";
			};

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			pwm0: pwm@f002c000 {
				compatible = "atmel,sama5d3-pwm";
				reg = <0xf002c000 0x300>;
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
				#pwm-cells = <3>;
				clocks = <&pwm_clk>;
				status = "disabled";
			};
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			isi: isi@f0034000 {
				compatible = "atmel,at91sam9g45-isi";
				reg = <0xf0034000 0x4000>;
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				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_isi_data_0_7>;
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				clocks = <&isi_clk>;
				clock-names = "isi_clk";
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				status = "disabled";
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				port {
					#address-cells = <1>;
					#size-cells = <0>;
				};
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			};

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			sfr: sfr@f0038000 {
				compatible = "atmel,sama5d3-sfr", "syscon";
				reg = <0xf0038000 0x60>;
			};

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			mmc1: mmc@f8000000 {
				compatible = "atmel,hsmci";
				reg = <0xf8000000 0x600>;
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				interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
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				dma-names = "rxtx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
				status = "disabled";
				#address-cells = <1>;
				#size-cells = <0>;
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				clocks = <&mci1_clk>;
				clock-names = "mci_clk";
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			};

			spi1: spi@f8008000 {
				#address-cells = <1>;
				#size-cells = <0>;
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				compatible = "atmel,at91rm9200-spi";
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				reg = <0xf8008000 0x100>;
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				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
				       <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi1>;
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				clocks = <&spi1_clk>;
				clock-names = "spi_clk";
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				status = "disabled";
			};

			ssc1: ssc@f800c000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf800c000 0x4000>;
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				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
				       <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
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				clocks = <&ssc1_clk>;
				clock-names = "pclk";
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				status = "disabled";
			};

			adc0: adc@f8018000 {
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				#address-cells = <1>;
				#size-cells = <0>;
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				compatible = "atmel,at91sam9x5-adc";
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				reg = <0xf8018000 0x100>;
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				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
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				pinctrl-names = "default";
				pinctrl-0 = <
					&pinctrl_adc0_adtrg
					&pinctrl_adc0_ad0
					&pinctrl_adc0_ad1
					&pinctrl_adc0_ad2
					&pinctrl_adc0_ad3
					&pinctrl_adc0_ad4
					&pinctrl_adc0_ad5
					&pinctrl_adc0_ad6
					&pinctrl_adc0_ad7
					&pinctrl_adc0_ad8
					&pinctrl_adc0_ad9
					&pinctrl_adc0_ad10
					&pinctrl_adc0_ad11
					>;
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				clocks = <&adc_clk>,
					 <&adc_op_clk>;
				clock-names = "adc_clk", "adc_op_clk";
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				atmel,adc-channels-used = <0xfff>;
				atmel,adc-startup-time = <40>;
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				atmel,adc-use-external-triggers;
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				atmel,adc-vref = <3000>;
				atmel,adc-res = <10 12>;
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				atmel,adc-sample-hold-time = <11>;
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				atmel,adc-res-names = "lowres", "highres";
				status = "disabled";

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				trigger0 {
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					trigger-name = "external-rising";
					trigger-value = <0x1>;
					trigger-external;
				};
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				trigger1 {
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					trigger-name = "external-falling";
					trigger-value = <0x2>;
					trigger-external;
				};
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				trigger2 {
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					trigger-name = "external-any";
					trigger-value = <0x3>;
					trigger-external;
				};
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				trigger3 {
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					trigger-name = "continuous";
					trigger-value = <0x6>;
				};
			};

			i2c2: i2c@f801c000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf801c000 0x4000>;
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				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
				       <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
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				dma-names = "tx", "rx";
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				pinctrl-names = "default", "gpio";
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				pinctrl-0 = <&pinctrl_i2c2>;
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				pinctrl-1 = <&pinctrl_i2c2_gpio>;
				sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioA 19 GPIO_ACTIVE_HIGH>;
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				#address-cells = <1>;
				#size-cells = <0>;
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				clocks = <&twi2_clk>;
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				status = "disabled";
			};

			usart2: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x100>;
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				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
				       <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart2>;
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				clocks = <&usart2_clk>;
				clock-names = "usart";
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				status = "disabled";
			};

			usart3: serial@f8024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8024000 0x100>;
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				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
				       <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart3>;
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				clocks = <&usart3_clk>;
				clock-names = "usart";
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				status = "disabled";
			};

			sha@f8034000 {
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				compatible = "atmel,at91sam9g46-sha";
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				reg = <0xf8034000 0x100>;
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				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
				dma-names = "tx";
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				clocks = <&sha_clk>;
				clock-names = "sha_clk";
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			};

			aes@f8038000 {
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				compatible = "atmel,at91sam9g46-aes";
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				reg = <0xf8038000 0x100>;
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				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
				       <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
				dma-names = "tx", "rx";
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				clocks = <&aes_clk>;
				clock-names = "aes_clk";
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			};

			tdes@f803c000 {
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				compatible = "atmel,at91sam9g46-tdes";
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				reg = <0xf803c000 0x100>;
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				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
				       <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
				dma-names = "tx", "rx";
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				clocks = <&tdes_clk>;
				clock-names = "tdes_clk";
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			};

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			trng@f8040000 {
				compatible = "atmel,at91sam9g45-trng";
				reg = <0xf8040000 0x100>;
				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&trng_clk>;
			};

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			hsmc: hsmc@ffffc000 {
				compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
				reg = <0xffffc000 0x1000>;
				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
				clocks = <&hsmc_clk>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				pmecc: ecc-engine@ffffc070 {
					compatible = "atmel,at91sam9g45-pmecc";
					reg = <0xffffc070 0x490>,
					      <0xffffc500 0x100>;
				};
			};

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			dma0: dma-controller@ffffe600 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffe600 0x200>;
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				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
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				#dma-cells = <2>;
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				clocks = <&dma0_clk>;
				clock-names = "dma_clk";
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			};

			dma1: dma-controller@ffffe800 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffe800 0x200>;
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				interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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				#dma-cells = <2>;
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				clocks = <&dma1_clk>;
				clock-names = "dma_clk";
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			};

			ramc0: ramc@ffffea00 {
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				compatible = "atmel,sama5d3-ddramc";
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				reg = <0xffffea00 0x200>;
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				clocks = <&ddrck>, <&mpddr_clk>;
				clock-names = "ddrck", "mpddr";
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			};

			dbgu: serial@ffffee00 {
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				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
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				reg = <0xffffee00 0x200>;
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				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
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				dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
				       <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
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				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
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				clocks = <&dbgu_clk>;
				clock-names = "usart";
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				status = "disabled";
			};

			aic: interrupt-controller@fffff000 {
				#interrupt-cells = <3>;
				compatible = "atmel,sama5d3-aic";
				interrupt-controller;
				reg = <0xfffff000 0x200>;
				atmel,external-irqs = <47>;
			};

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			pinctrl: pinctrl@fffff200 {
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				#address-cells = <1>;
				#size-cells = <1>;
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				compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
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				ranges = <0xfffff200 0xfffff200 0xa00>;
				atmel,mux-mask = <
					/*   A          B          C  */
					0xffffffff 0xc0fc0000 0xc0ff0000	/* pioA */
					0xffffffff 0x0ff8ffff 0x00000000	/* pioB */
					0xffffffff 0xbc00f1ff 0x7c00fc00	/* pioC */
					0xffffffff 0xc001c0e0 0x0001c1e0	/* pioD */
					0xffffffff 0xbf9f8000 0x18000000	/* pioE */
					>;

				/* shared pinctrl settings */
				adc0 {
					pinctrl_adc0_adtrg: adc0_adtrg {
						atmel,pins =
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							<AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD19 periph A ADTRG */
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					};
					pinctrl_adc0_ad0: adc0_ad0 {
						atmel,pins =
529
							<AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD20 periph A AD0 */
530 531 532
					};
					pinctrl_adc0_ad1: adc0_ad1 {
						atmel,pins =
533
							<AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD21 periph A AD1 */
534 535 536
					};
					pinctrl_adc0_ad2: adc0_ad2 {
						atmel,pins =
537
							<AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD22 periph A AD2 */
538 539 540
					};
					pinctrl_adc0_ad3: adc0_ad3 {
						atmel,pins =
541
							<AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD23 periph A AD3 */
542 543 544
					};
					pinctrl_adc0_ad4: adc0_ad4 {
						atmel,pins =
545
							<AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD24 periph A AD4 */
546 547 548
					};
					pinctrl_adc0_ad5: adc0_ad5 {
						atmel,pins =
549
							<AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD25 periph A AD5 */
550 551 552
					};
					pinctrl_adc0_ad6: adc0_ad6 {
						atmel,pins =
553
							<AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD26 periph A AD6 */
554 555 556
					};
					pinctrl_adc0_ad7: adc0_ad7 {
						atmel,pins =
557
							<AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD27 periph A AD7 */
558 559 560
					};
					pinctrl_adc0_ad8: adc0_ad8 {
						atmel,pins =
561
							<AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD28 periph A AD8 */
562 563 564
					};
					pinctrl_adc0_ad9: adc0_ad9 {
						atmel,pins =
565
							<AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD29 periph A AD9 */
566 567 568
					};
					pinctrl_adc0_ad10: adc0_ad10 {
						atmel,pins =
569
							<AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD30 periph A AD10, conflicts with PCK0 */
570 571 572
					};
					pinctrl_adc0_ad11: adc0_ad11 {
						atmel,pins =
573
							<AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD31 periph A AD11, conflicts with PCK1 */
574 575 576 577 578 579
					};
				};

				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
580 581
							<AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
							 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
582 583 584
					};
				};

585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644
				ebi {
					pinctrl_ebi_addr: ebi-addr-0 {
						atmel,pins =
							<AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nand_addr: ebi-addr-1 {
						atmel,pins =
							<AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs0: ebi-cs0-0 {
						atmel,pins =
							<AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs1: ebi-cs1-0 {
						atmel,pins =
							<AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs2: ebi-cs2-0 {
						atmel,pins =
							<AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nwait: ebi-nwait-0 {
						atmel,pins =
							<AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
						atmel,pins =
							<AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

645 646 647
				i2c0 {
					pinctrl_i2c0: i2c0-0 {
						atmel,pins =
648 649
							<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
							 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
650
					};
651 652 653 654 655 656

					pinctrl_i2c0_gpio: i2c0-gpio {
						atmel,pins =
							<AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
657 658 659 660 661
				};

				i2c1 {
					pinctrl_i2c1: i2c1-0 {
						atmel,pins =
662 663
							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
664
					};
665 666 667 668 669 670

					pinctrl_i2c1_gpio: i2c1-gpio {
						atmel,pins =
							<AT91_PIOC 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOC 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
671 672
				};

673 674 675 676 677 678
				i2c2 {
					pinctrl_i2c2: i2c2-0 {
						atmel,pins =
							<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
							 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
					};
679 680 681 682 683 684

					pinctrl_i2c2_gpio: i2c2-gpio {
						atmel,pins =
							<AT91_PIOA 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOA 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
685 686
				};

687
				isi {
688
					pinctrl_isi_data_0_7: isi-0-data-0-7 {
689
						atmel,pins =
690 691 692 693 694 695 696 697 698 699
							<AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
							 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
							 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
							 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
							 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
							 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
							 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
							 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
							 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC30 periph C ISI_PCK, conflicts with UTXD0 */
							 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
700 701 702 703 704 705
							 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
					};

					pinctrl_isi_data_8_9: isi-0-data-8-9 {
						atmel,pins =
							<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
706
							 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
707
					};
708

709 710 711 712 713
					pinctrl_isi_data_10_11: isi-0-data-10-11 {
						atmel,pins =
							<AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
							 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
					};
714 715 716 717 718
				};

				mmc0 {
					pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
						atmel,pins =
719 720 721
							<AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD9 periph A MCI0_CK */
							 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PD0 periph A MCI0_CDA with pullup */
							 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PD1 periph A MCI0_DA0 with pullup */
722 723 724
					};
					pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
						atmel,pins =
725 726 727
							<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PD2 periph A MCI0_DA1 with pullup */
							 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PD3 periph A MCI0_DA2 with pullup */
							 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PD4 periph A MCI0_DA3 with pullup */
728 729 730
					};
					pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
						atmel,pins =
731 732 733 734
							<AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
							 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
							 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
							 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
735 736 737 738 739 740
					};
				};

				mmc1 {
					pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
						atmel,pins =
741 742 743
							<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB24 periph A MCI1_CK, conflicts with GRX5 */
							 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
							 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
744 745 746
					};
					pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
						atmel,pins =
747 748 749
							<AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
							 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
							 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
750 751 752 753 754 755
					};
				};

				nand0 {
					pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
						atmel,pins =
756 757
							<AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PE21 periph A with pullup */
							 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PE22 periph A with pullup */
758 759 760
					};
				};

761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838
				pwm0 {
					pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
						atmel,pins =
							<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with ISI_D4 and LCDDAT20 */
					};
					pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
						atmel,pins =
							<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with GTX0 */
					};
					pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
						atmel,pins =
							<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with ISI_D5 and LCDDAT21 */
					};
					pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
						atmel,pins =
							<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with GTX1 */
					};

					pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
						atmel,pins =
							<AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with ISI_D6 and LCDDAT22 */
					};
					pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
						atmel,pins =
							<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with GRX0 */
					};
					pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
						atmel,pins =
							<AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* conflicts with G125CKO and RTS1 */
					};
					pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
						atmel,pins =
							<AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with ISI_D7 and LCDDAT23 */
					};
					pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
						atmel,pins =
							<AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with GRX1 */
					};
					pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
						atmel,pins =
							<AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with IRQ */
					};

					pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
						atmel,pins =
							<AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with GTXCK */
					};
					pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
						atmel,pins =
							<AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* conflicts with MCI0_DA4 and TIOA0 */
					};
					pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
						atmel,pins =
							<AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with GTXEN */
					};
					pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
						atmel,pins =
							<AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* conflicts with MCI0_DA5 and TIOB0 */
					};

					pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
						atmel,pins =
							<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with GRXDV */
					};
					pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
						atmel,pins =
							<AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* conflicts with MCI0_DA6 and TCLK0 */
					};
					pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
						atmel,pins =
							<AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with GRXER */
					};
					pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
						atmel,pins =
							<AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* conflicts with MCI0_DA7 */
					};
				};

839 840 841
				spi0 {
					pinctrl_spi0: spi0-0 {
						atmel,pins =
842 843 844
							<AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD10 periph A SPI0_MISO pin */
							 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD11 periph A SPI0_MOSI pin */
							 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD12 periph A SPI0_SPCK pin */
845 846 847 848 849 850
					};
				};

				spi1 {
					pinctrl_spi1: spi1-0 {
						atmel,pins =
851 852 853
							<AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC22 periph A SPI1_MISO pin */
							 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC23 periph A SPI1_MOSI pin */
							 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PC24 periph A SPI1_SPCK pin */
854 855 856 857 858 859
					};
				};

				ssc0 {
					pinctrl_ssc0_tx: ssc0_tx {
						atmel,pins =
860 861 862
							<AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC16 periph A TK0 */
							 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC17 periph A TF0 */
							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PC18 periph A TD0 */
863 864 865 866
					};

					pinctrl_ssc0_rx: ssc0_rx {
						atmel,pins =
867 868 869
							<AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC19 periph A RK0 */
							 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC20 periph A RF0 */
							 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PC21 periph A RD0 */
870 871 872 873 874 875
					};
				};

				ssc1 {
					pinctrl_ssc1_tx: ssc1_tx {
						atmel,pins =
876 877 878
							<AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB2 periph B TK1, conflicts with GTX2 */
							 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB3 periph B TF1, conflicts with GTX3 */
							 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB6 periph B TD1, conflicts with TD1 */
879 880 881 882
					};

					pinctrl_ssc1_rx: ssc1_rx {
						atmel,pins =
883 884 885
							<AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB7 periph B RK1, conflicts with EREFCK */
							 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB10 periph B RF1, conflicts with GTXER */
							 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB11 periph B RD1, conflicts with GRXCK */
886 887 888
					};
				};

889 890 891
				uart0 {
					pinctrl_uart0: uart0-0 {
						atmel,pins =
892 893
							<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* conflicts with PWMFI2, ISI_D8 */
							 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* conflicts with ISI_PCK */
894 895 896
					};
				};

897 898 899
				uart1 {
					pinctrl_uart1: uart1-0 {
						atmel,pins =
900 901
							<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* conflicts with TWD0, ISI_VSYNC */
							 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with TWCK0, ISI_HSYNC */
902 903 904
					};
				};

905 906 907
				usart0 {
					pinctrl_usart0: usart0-0 {
						atmel,pins =
908 909
							<AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
							 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
910 911 912 913
					};

					pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
						atmel,pins =
914 915
							<AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
							 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
916 917 918 919 920 921
					};
				};

				usart1 {
					pinctrl_usart1: usart1-0 {
						atmel,pins =
922 923
							<AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
							 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
924 925 926 927
					};

					pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
						atmel,pins =
928 929
							<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB26 periph A, conflicts with GRX7 */
							 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB27 periph A, conflicts with G125CKO */
930 931 932 933 934 935
					};
				};

				usart2 {
					pinctrl_usart2: usart2-0 {
						atmel,pins =
936 937
							<AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* conflicts with A25 */
							 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts NCS0 */
938 939 940 941
					};

					pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
						atmel,pins =
942 943
							<AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PE23 periph B, conflicts with A23 */
							 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PE24 periph B, conflicts with A24 */
944 945 946 947 948 949
					};
				};

				usart3 {
					pinctrl_usart3: usart3-0 {
						atmel,pins =
950 951
							<AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* conflicts with A18 */
							 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with A19 */
952 953 954 955
					};

					pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
						atmel,pins =
956 957
							<AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PE16 periph B, conflicts with A16 */
							 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PE17 periph B, conflicts with A17 */
958 959
					};
				};
960 961 962 963 964


				pioA: gpio@fffff200 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff200 0x100>;
965
					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
966 967 968 969
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
970
					clocks = <&pioA_clk>;
971 972 973 974 975
				};

				pioB: gpio@fffff400 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff400 0x100>;
976
					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
977 978 979 980
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
981
					clocks = <&pioB_clk>;
982 983 984 985 986
				};

				pioC: gpio@fffff600 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff600 0x100>;
987
					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
988 989 990 991
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
992
					clocks = <&pioC_clk>;
993 994 995 996 997
				};

				pioD: gpio@fffff800 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff800 0x100>;
998
					interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
999 1000 1001 1002
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
1003
					clocks = <&pioD_clk>;
1004 1005 1006 1007 1008
				};

				pioE: gpio@fffffa00 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffffa00 0x100>;
1009
					interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
1010 1011 1012 1013
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
1014
					clocks = <&pioE_clk>;
1015
				};
1016 1017 1018
			};

			pmc: pmc@fffffc00 {
1019
				compatible = "atmel,sama5d3-pmc", "syscon";
1020
				reg = <0xfffffc00 0x120>;
1021 1022 1023 1024 1025 1026
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;
				#interrupt-cells = <1>;

1027 1028
				main_rc_osc: main_rc_osc {
					compatible = "atmel,at91sam9x5-clk-main-rc-osc";
1029
					#clock-cells = <0>;
1030 1031 1032 1033
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_MOSCRCS>;
					clock-frequency = <12000000>;
					clock-accuracy = <50000000>;
1034 1035
				};

1036 1037
				main_osc: main_osc {
					compatible = "atmel,at91rm9200-clk-main-osc";
1038 1039 1040
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_MOSCS>;
1041 1042 1043 1044 1045 1046 1047 1048 1049
					clocks = <&main_xtal>;
				};

				main: mainck {
					compatible = "atmel,at91sam9x5-clk-main";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_MOSCSELS>;
					clocks = <&main_rc_osc &main_osc>;
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184
				};

				plla: pllack {
					compatible = "atmel,sama5d3-clk-pll";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_LOCKA>;
					clocks = <&main>;
					reg = <0>;
					atmel,clk-input-range = <8000000 50000000>;
					#atmel,pll-clk-output-range-cells = <4>;
					atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
				};

				plladiv: plladivck {
					compatible = "atmel,at91sam9x5-clk-plldiv";
					#clock-cells = <0>;
					clocks = <&plla>;
				};

				utmi: utmick {
					compatible = "atmel,at91sam9x5-clk-utmi";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_LOCKU>;
					clocks = <&main>;
				};

				mck: masterck {
					compatible = "atmel,at91sam9x5-clk-master";
					#clock-cells = <0>;
					interrupt-parent = <&pmc>;
					interrupts = <AT91_PMC_MCKRDY>;
					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
					atmel,clk-output-range = <0 166000000>;
					atmel,clk-divisors = <1 2 4 3>;
				};

				usb: usbck {
					compatible = "atmel,at91sam9x5-clk-usb";
					#clock-cells = <0>;
					clocks = <&plladiv>, <&utmi>;
				};

				prog: progck {
					compatible = "atmel,at91sam9x5-clk-programmable";
					#address-cells = <1>;
					#size-cells = <0>;
					interrupt-parent = <&pmc>;
					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;

					prog0: prog0 {
						#clock-cells = <0>;
						reg = <0>;
						interrupts = <AT91_PMC_PCKRDY(0)>;
					};

					prog1: prog1 {
						#clock-cells = <0>;
						reg = <1>;
						interrupts = <AT91_PMC_PCKRDY(1)>;
					};

					prog2: prog2 {
						#clock-cells = <0>;
						reg = <2>;
						interrupts = <AT91_PMC_PCKRDY(2)>;
					};
				};

				smd: smdclk {
					compatible = "atmel,at91sam9x5-clk-smd";
					#clock-cells = <0>;
					clocks = <&plladiv>, <&utmi>;
				};

				systemck {
					compatible = "atmel,at91rm9200-clk-system";
					#address-cells = <1>;
					#size-cells = <0>;

					ddrck: ddrck {
						#clock-cells = <0>;
						reg = <2>;
						clocks = <&mck>;
					};

					smdck: smdck {
						#clock-cells = <0>;
						reg = <4>;
						clocks = <&smd>;
					};

					uhpck: uhpck {
						#clock-cells = <0>;
						reg = <6>;
						clocks = <&usb>;
					};

					udpck: udpck {
						#clock-cells = <0>;
						reg = <7>;
						clocks = <&usb>;
					};

					pck0: pck0 {
						#clock-cells = <0>;
						reg = <8>;
						clocks = <&prog0>;
					};

					pck1: pck1 {
						#clock-cells = <0>;
						reg = <9>;
						clocks = <&prog1>;
					};

					pck2: pck2 {
						#clock-cells = <0>;
						reg = <10>;
						clocks = <&prog2>;
					};
				};

				periphck {
					compatible = "atmel,at91sam9x5-clk-peripheral";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&mck>;

					dbgu_clk: dbgu_clk {
						#clock-cells = <0>;
						reg = <2>;
					};

1185 1186 1187 1188 1189
					hsmc_clk: hsmc_clk {
						#clock-cells = <0>;
						reg = <5>;
					};

1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217
					pioA_clk: pioA_clk {
						#clock-cells = <0>;
						reg = <6>;
					};

					pioB_clk: pioB_clk {
						#clock-cells = <0>;
						reg = <7>;
					};

					pioC_clk: pioC_clk {
						#clock-cells = <0>;
						reg = <8>;
					};

					pioD_clk: pioD_clk {
						#clock-cells = <0>;
						reg = <9>;
					};

					pioE_clk: pioE_clk {
						#clock-cells = <0>;
						reg = <10>;
					};

					usart0_clk: usart0_clk {
						#clock-cells = <0>;
						reg = <12>;
1218
						atmel,clk-output-range = <0 83000000>;
1219 1220 1221 1222 1223
					};

					usart1_clk: usart1_clk {
						#clock-cells = <0>;
						reg = <13>;
1224
						atmel,clk-output-range = <0 83000000>;
1225 1226 1227 1228 1229
					};

					usart2_clk: usart2_clk {
						#clock-cells = <0>;
						reg = <14>;
1230
						atmel,clk-output-range = <0 83000000>;
1231 1232 1233 1234 1235
					};

					usart3_clk: usart3_clk {
						#clock-cells = <0>;
						reg = <15>;
1236
						atmel,clk-output-range = <0 83000000>;
1237 1238
					};

1239 1240 1241
					uart0_clk: uart0_clk {
						#clock-cells = <0>;
						reg = <16>;
1242
						atmel,clk-output-range = <0 83000000>;
1243 1244
					};

1245 1246 1247
					twi0_clk: twi0_clk {
						reg = <18>;
						#clock-cells = <0>;
1248
						atmel,clk-output-range = <0 41500000>;
1249 1250 1251 1252 1253
					};

					twi1_clk: twi1_clk {
						#clock-cells = <0>;
						reg = <19>;
1254
						atmel,clk-output-range = <0 41500000>;
1255 1256 1257 1258 1259
					};

					twi2_clk: twi2_clk {
						#clock-cells = <0>;
						reg = <20>;
1260
						atmel,clk-output-range = <0 41500000>;
1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275
					};

					mci0_clk: mci0_clk {
						#clock-cells = <0>;
						reg = <21>;
					};

					mci1_clk: mci1_clk {
						#clock-cells = <0>;
						reg = <22>;
					};

					spi0_clk: spi0_clk {
						#clock-cells = <0>;
						reg = <24>;
1276
						atmel,clk-output-range = <0 166000000>;
1277 1278 1279 1280 1281
					};

					spi1_clk: spi1_clk {
						#clock-cells = <0>;
						reg = <25>;
1282
						atmel,clk-output-range = <0 166000000>;
1283 1284 1285 1286 1287
					};

					tcb0_clk: tcb0_clk {
						#clock-cells = <0>;
						reg = <26>;
1288
						atmel,clk-output-range = <0 166000000>;
1289 1290 1291 1292 1293 1294 1295 1296 1297 1298
					};

					pwm_clk: pwm_clk {
						#clock-cells = <0>;
						reg = <28>;
					};

					adc_clk: adc_clk {
						#clock-cells = <0>;
						reg = <29>;
1299
						atmel,clk-output-range = <0 83000000>;
1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329
					};

					dma0_clk: dma0_clk {
						#clock-cells = <0>;
						reg = <30>;
					};

					dma1_clk: dma1_clk {
						#clock-cells = <0>;
						reg = <31>;
					};

					uhphs_clk: uhphs_clk {
						#clock-cells = <0>;
						reg = <32>;
					};

					udphs_clk: udphs_clk {
						#clock-cells = <0>;
						reg = <33>;
					};

					isi_clk: isi_clk {
						#clock-cells = <0>;
						reg = <37>;
					};

					ssc0_clk: ssc0_clk {
						#clock-cells = <0>;
						reg = <38>;
1330
						atmel,clk-output-range = <0 83000000>;
1331 1332 1333 1334 1335
					};

					ssc1_clk: ssc1_clk {
						#clock-cells = <0>;
						reg = <39>;
1336
						atmel,clk-output-range = <0 83000000>;
1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362
					};

					sha_clk: sha_clk {
						#clock-cells = <0>;
						reg = <42>;
					};

					aes_clk: aes_clk {
						#clock-cells = <0>;
						reg = <43>;
					};

					tdes_clk: tdes_clk {
						#clock-cells = <0>;
						reg = <44>;
					};

					trng_clk: trng_clk {
						#clock-cells = <0>;
						reg = <45>;
					};

					fuse_clk: fuse_clk {
						#clock-cells = <0>;
						reg = <48>;
					};
1363 1364 1365 1366 1367

					mpddr_clk: mpddr_clk {
						#clock-cells = <0>;
						reg = <49>;
					};
1368
				};
1369 1370
			};

1371
			reset_controller: rstc@fffffe00 {
1372
				compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
1373
				reg = <0xfffffe00 0x10>;
1374
				clocks = <&clk32k>;
1375 1376
			};

1377
			shutdown_controller: shutdown-controller@fffffe10 {
1378 1379
				compatible = "atmel,at91sam9x5-shdwc";
				reg = <0xfffffe10 0x10>;
1380
				clocks = <&clk32k>;
1381 1382
			};

1383 1384 1385
			pit: timer@fffffe30 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffe30 0xf>;
1386
				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1387
				clocks = <&mck>;
1388 1389
			};

1390
			watchdog: watchdog@fffffe40 {
1391 1392
				compatible = "atmel,at91sam9260-wdt";
				reg = <0xfffffe40 0x10>;
1393
				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1394
				clocks = <&clk32k>;
1395 1396 1397
				atmel,watchdog-type = "hardware";
				atmel,reset-type = "all";
				atmel,dbg-halt;
1398 1399 1400
				status = "disabled";
			};

1401 1402
			clk32k: sckc@fffffe50 {
				compatible = "atmel,sama5d3-sckc";
1403
				reg = <0xfffffe50 0x4>;
1404 1405
				clocks = <&slow_xtal>;
				#clock-cells = <0>;
1406 1407
			};

1408 1409 1410
			rtc@fffffeb0 {
				compatible = "atmel,at91rm9200-rtc";
				reg = <0xfffffeb0 0x30>;
1411
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1412
				clocks = <&clk32k>;
1413 1414 1415
			};
		};

1416 1417 1418 1419 1420 1421
		nfc_sram: sram@200000 {
			compatible = "mmio-sram";
			no-memory-wc;
			reg = <0x200000 0x2400>;
		};

1422
		usb0: gadget@500000 {
1423 1424
			#address-cells = <1>;
			#size-cells = <0>;
1425
			compatible = "atmel,sama5d3-udc";
1426 1427
			reg = <0x00500000 0x100000
			       0xf8030000 0x4000>;
1428
			interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
1429 1430
			clocks = <&udphs_clk>, <&utmi>;
			clock-names = "pclk", "hclk";
1431 1432
			status = "disabled";

1433
			ep@0 {
1434 1435 1436 1437 1438
				reg = <0>;
				atmel,fifo-size = <64>;
				atmel,nb-banks = <1>;
			};

1439
			ep@1 {
1440 1441 1442 1443 1444 1445 1446
				reg = <1>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <3>;
				atmel,can-dma;
				atmel,can-isoc;
			};

1447
			ep@2 {
1448 1449 1450 1451 1452 1453 1454
				reg = <2>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <3>;
				atmel,can-dma;
				atmel,can-isoc;
			};

1455
			ep@3 {
1456 1457 1458 1459 1460 1461
				reg = <3>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
			};

1462
			ep@4 {
1463 1464 1465 1466 1467 1468
				reg = <4>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
			};

1469
			ep@5 {
1470 1471 1472 1473 1474 1475
				reg = <5>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
			};

1476
			ep@6 {
1477 1478 1479 1480 1481 1482
				reg = <6>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
			};

1483
			ep@7 {
1484 1485 1486 1487 1488 1489
				reg = <7>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
				atmel,can-dma;
			};

1490
			ep@8 {
1491 1492 1493 1494 1495
				reg = <8>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
			};

1496
			ep@9 {
1497 1498 1499 1500 1501
				reg = <9>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
			};

1502
			ep@10 {
1503 1504 1505 1506 1507
				reg = <10>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
			};

1508
			ep@11 {
1509 1510 1511 1512 1513
				reg = <11>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
			};

1514
			ep@12 {
1515 1516 1517 1518 1519
				reg = <12>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
			};

1520
			ep@13 {
1521 1522 1523 1524 1525
				reg = <13>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
			};

1526
			ep@14 {
1527 1528 1529 1530 1531
				reg = <14>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
			};

1532
			ep@15 {
1533 1534 1535 1536 1537 1538
				reg = <15>;
				atmel,fifo-size = <1024>;
				atmel,nb-banks = <2>;
			};
		};

1539
		usb1: ohci@600000 {
1540 1541
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00600000 0x100000>;
1542
			interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1543 1544
			clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
			clock-names = "ohci_clk", "hclk", "uhpck";
1545 1546 1547
			status = "disabled";
		};

1548
		usb2: ehci@700000 {
1549 1550
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00700000 0x100000>;
1551
			interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1552 1553
			clocks = <&utmi>, <&uhphs_clk>;
			clock-names = "usb_clk", "ehci_clk";
1554 1555 1556
			status = "disabled";
		};

1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586
		ebi: ebi@10000000 {
			compatible = "atmel,sama5d3-ebi";
			#address-cells = <2>;
			#size-cells = <1>;
			atmel,smc = <&hsmc>;
			reg = <0x10000000 0x10000000
			       0x40000000 0x30000000>;
			ranges = <0x0 0x0 0x10000000 0x10000000
				  0x1 0x0 0x40000000 0x10000000
				  0x2 0x0 0x50000000 0x10000000
				  0x3 0x0 0x60000000 0x10000000>;
			clocks = <&mck>;
			status = "disabled";

			nand_controller: nand-controller {
				compatible = "atmel,sama5d3-nand-controller";
				atmel,nfc-sram = <&nfc_sram>;
				atmel,nfc-io = <&nfc_io>;
				ecc-engine = <&pmecc>;
				#address-cells = <2>;
				#size-cells = <1>;
				ranges;
				status = "disabled";
			};
		};

		nfc_io: nfc-io@70000000 {
			compatible = "atmel,sama5d3-nfc-io", "syscon";
			reg = <0x70000000 0x8000000>;
		};
1587 1588
	};
};