clockdomains2xxx_3xxx_data.c 20.9 KB
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/*
 * OMAP2/3 clockdomains
 *
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 * Copyright (C) 2008-2009 Texas Instruments, Inc.
 * Copyright (C) 2008-2010 Nokia Corporation
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 *
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 * Paul Walmsley, Jouni Högander
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 *
 * This file contains clockdomains and clockdomain wakeup/sleep
 * dependencies for the OMAP2/3 chips.  Some notes:
 *
 * A useful validation rule for struct clockdomain: Any clockdomain
 * referenced by a wkdep_srcs or sleepdep_srcs array must have a
 * dep_bit assigned.  So wkdep_srcs/sleepdep_srcs are really just
 * software-controllable dependencies.  Non-software-controllable
 * dependencies do exist, but they are not encoded below (yet).
 *
 * 24xx does not support programmable sleep dependencies (SLEEPDEP)
 *
 * The overly-specific dep_bit names are due to a bit name collision
 * with CM_FCLKEN_{DSP,IVA2}.  The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
 * value are the same for all powerdomains: 2
 *
 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
 * sanity check?
 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
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 */

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/*
 * To-Do List
 * -> Port the Sleep/Wakeup dependencies for the domains
 *    from the Power domain framework
 */

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#include <linux/kernel.h>
#include <linux/io.h>
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#include "clockdomain.h"
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#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#include "cm-regbits-44xx.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h"
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/*
 * Clockdomain dependencies for wkdeps/sleepdeps
 *
 * XXX Hardware dependencies (e.g., dependencies that cannot be
 * changed in software) are not included here yet, but should be.
 */

/* OMAP2/3-common wakeup dependencies */

/*
 * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
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 * These can share data since they will never be present simultaneously
 * on the same device.
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 */
static struct clkdm_dep gfx_sgx_wkdeps[] = {
	{
		.clkdm_name = "core_l3_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "core_l4_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
					    CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
					    CHIP_IS_OMAP3430)
	},
	{ NULL },
};


/* 24XX-specific possible dependencies */

/* Wakeup dependency source arrays */

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/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
static struct clkdm_dep dsp_24xx_wkdeps[] = {
	{
		.clkdm_name = "core_l3_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "core_l4_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{ NULL },
};

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/*
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 * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
 * 2430 adds MDM
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 */
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static struct clkdm_dep mpu_24xx_wkdeps[] = {
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	{
		.clkdm_name = "core_l3_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "core_l4_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
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		.clkdm_name = "dsp_clkdm",
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		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
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	{
		.clkdm_name = "mdm_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
	},
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	{ NULL },
};

/*
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 * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
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 * 2430 adds MDM
 */
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static struct clkdm_dep core_24xx_wkdeps[] = {
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	{
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		.clkdm_name = "dsp_clkdm",
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		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
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		.clkdm_name = "gfx_clkdm",
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		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
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		.clkdm_name = "mpu_clkdm",
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		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "mdm_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
	},
	{ NULL },
};

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/* 2430-specific possible wakeup dependencies */

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#ifdef CONFIG_SOC_OMAP2430
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/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
static struct clkdm_dep mdm_2430_wkdeps[] = {
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	{
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		.clkdm_name = "core_l3_clkdm",
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		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
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		.clkdm_name = "core_l4_clkdm",
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		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
	},
	{ NULL },
};

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#endif /* CONFIG_SOC_OMAP2430 */
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/* OMAP3-specific possible dependencies */
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#ifdef CONFIG_ARCH_OMAP3
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/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
static struct clkdm_dep per_wkdeps[] = {
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	{
		.clkdm_name = "core_l3_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "core_l4_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

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/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
static struct clkdm_dep usbhost_wkdeps[] = {
	{
		.clkdm_name = "core_l3_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "core_l4_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
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static struct clkdm_dep mpu_3xxx_wkdeps[] = {
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	{
		.clkdm_name = "core_l3_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "core_l4_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "dss_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "per_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

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/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
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static struct clkdm_dep iva2_wkdeps[] = {
	{
		.clkdm_name = "core_l3_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "core_l4_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "dss_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "per_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};


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/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
static struct clkdm_dep cam_wkdeps[] = {
	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
static struct clkdm_dep dss_wkdeps[] = {
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	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "wkup_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

/* 3430: PM_WKDEP_NEON: MPU */
static struct clkdm_dep neon_wkdeps[] = {
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};


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/* Sleep dependency source arrays for OMAP3-specific clkdms */
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/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
static struct clkdm_dep dss_sleepdeps[] = {
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	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

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/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
static struct clkdm_dep per_sleepdeps[] = {
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
static struct clkdm_dep usbhost_sleepdeps[] = {
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
		.clkdm_name = "iva2_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

/* 3430: CM_SLEEPDEP_CAM: MPU */
static struct clkdm_dep cam_sleepdeps[] = {
	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

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/*
 * 3430ES1: CM_SLEEPDEP_GFX: MPU
 * 3430ES2: CM_SLEEPDEP_SGX: MPU
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 * These can share data since they will never be present simultaneously
 * on the same device.
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 */
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static struct clkdm_dep gfx_sgx_sleepdeps[] = {
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	{
		.clkdm_name = "mpu_clkdm",
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{ NULL },
};

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#endif /* CONFIG_ARCH_OMAP3 */
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/*
 * OMAP2/3-common clockdomains
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 *
 * Even though the 2420 has a single PRCM module from the
 * interconnect's perspective, internally it does appear to have
 * separate PRM and CM clockdomains.  The usual test case is
 * sys_clkout/sys_clkout2.
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 */

/* This is an implicit clockdomain - it is never defined as such in TRM */
static struct clockdomain wkup_clkdm = {
	.name		= "wkup_clkdm",
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	.pwrdm		= { .name = "wkup_pwrdm" },
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	.dep_bit	= OMAP_EN_WKUP_SHIFT,
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};

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static struct clockdomain prm_clkdm = {
	.name		= "prm_clkdm",
	.pwrdm		= { .name = "wkup_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};

static struct clockdomain cm_clkdm = {
	.name		= "cm_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};

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/*
 * 2420-only clockdomains
 */

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#if defined(CONFIG_SOC_OMAP2420)
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static struct clockdomain mpu_2420_clkdm = {
	.name		= "mpu_clkdm",
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	.pwrdm		= { .name = "mpu_pwrdm" },
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	.flags		= CLKDM_CAN_HWSUP,
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	.wkdep_srcs	= mpu_24xx_wkdeps,
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	.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain iva1_2420_clkdm = {
	.name		= "iva1_clkdm",
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	.pwrdm		= { .name = "dsp_pwrdm" },
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	.flags		= CLKDM_CAN_HWSUP_SWSUP,
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	.dep_bit	= OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
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	.wkdep_srcs	= dsp_24xx_wkdeps,
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	.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

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static struct clockdomain dsp_2420_clkdm = {
	.name		= "dsp_clkdm",
	.pwrdm		= { .name = "dsp_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain gfx_2420_clkdm = {
	.name		= "gfx_clkdm",
	.pwrdm		= { .name = "gfx_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
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	.wkdep_srcs	= gfx_sgx_wkdeps,
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	.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain core_l3_2420_clkdm = {
	.name		= "core_l3_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
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	.wkdep_srcs	= core_24xx_wkdeps,
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	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain core_l4_2420_clkdm = {
	.name		= "core_l4_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
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	.wkdep_srcs	= core_24xx_wkdeps,
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	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

static struct clockdomain dss_2420_clkdm = {
	.name		= "dss_clkdm",
	.pwrdm		= { .name = "core_pwrdm" },
	.flags		= CLKDM_CAN_HWSUP,
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};

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#endif   /* CONFIG_SOC_OMAP2420 */
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/*
 * 2430-only clockdomains
 */

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#if defined(CONFIG_SOC_OMAP2430)
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static struct clockdomain mpu_2430_clkdm = {
	.name		= "mpu_clkdm",
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	.pwrdm		= { .name = "mpu_pwrdm" },
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	.flags		= CLKDM_CAN_HWSUP_SWSUP,
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	.wkdep_srcs	= mpu_24xx_wkdeps,
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	.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

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/* Another case of bit name collisions between several registers: EN_MDM */
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static struct clockdomain mdm_clkdm = {
	.name		= "mdm_clkdm",
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	.pwrdm		= { .name = "mdm_pwrdm" },
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	.flags		= CLKDM_CAN_HWSUP_SWSUP,
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	.dep_bit	= OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
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	.wkdep_srcs	= mdm_2430_wkdeps,
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	.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

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static struct clockdomain dsp_2430_clkdm = {
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	.name		= "dsp_clkdm",
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	.pwrdm		= { .name = "dsp_pwrdm" },
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	.flags		= CLKDM_CAN_HWSUP_SWSUP,
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	.dep_bit	= OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
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	.wkdep_srcs	= dsp_24xx_wkdeps,
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	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};

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static struct clockdomain gfx_2430_clkdm = {
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	.name		= "gfx_clkdm",
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	.pwrdm		= { .name = "gfx_pwrdm" },
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	.flags		= CLKDM_CAN_HWSUP_SWSUP,
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	.wkdep_srcs	= gfx_sgx_wkdeps,
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	.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};

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/*
 * XXX add usecounting for clkdm dependencies, otherwise the presence
 * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
 * could cause trouble
 */
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static struct clockdomain core_l3_2430_clkdm = {
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	.name		= "core_l3_clkdm",
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	.pwrdm		= { .name = "core_pwrdm" },
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	.flags		= CLKDM_CAN_HWSUP,
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	.dep_bit	= OMAP24XX_EN_CORE_SHIFT,
	.wkdep_srcs	= core_24xx_wkdeps,
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	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
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	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};

580 581 582 583 584
/*
 * XXX add usecounting for clkdm dependencies, otherwise the presence
 * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
 * could cause trouble
 */
585
static struct clockdomain core_l4_2430_clkdm = {
586
	.name		= "core_l4_clkdm",
587
	.pwrdm		= { .name = "core_pwrdm" },
588
	.flags		= CLKDM_CAN_HWSUP,
589 590
	.dep_bit	= OMAP24XX_EN_CORE_SHIFT,
	.wkdep_srcs	= core_24xx_wkdeps,
591
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
592
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
593 594
};

595
static struct clockdomain dss_2430_clkdm = {
596
	.name		= "dss_clkdm",
597
	.pwrdm		= { .name = "core_pwrdm" },
598 599
	.flags		= CLKDM_CAN_HWSUP,
	.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
600
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
601 602
};

603
#endif    /* CONFIG_SOC_OMAP2430 */
604 605 606


/*
607
 * OMAP3 clockdomains
608 609
 */

610
#if defined(CONFIG_ARCH_OMAP3)
611

612
static struct clockdomain mpu_3xxx_clkdm = {
613
	.name		= "mpu_clkdm",
614
	.pwrdm		= { .name = "mpu_pwrdm" },
615
	.flags		= CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
616
	.dep_bit	= OMAP3430_EN_MPU_SHIFT,
617
	.wkdep_srcs	= mpu_3xxx_wkdeps,
618 619 620 621 622 623
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain neon_clkdm = {
	.name		= "neon_clkdm",
624
	.pwrdm		= { .name = "neon_pwrdm" },
625
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
626
	.wkdep_srcs	= neon_wkdeps,
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	.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain iva2_clkdm = {
	.name		= "iva2_clkdm",
633
	.pwrdm		= { .name = "iva2_pwrdm" },
634
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
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	.dep_bit	= OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
	.wkdep_srcs	= iva2_wkdeps,
637 638 639 640 641 642
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain gfx_3430es1_clkdm = {
	.name		= "gfx_clkdm",
643
	.pwrdm		= { .name = "gfx_pwrdm" },
644
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
645
	.wkdep_srcs	= gfx_sgx_wkdeps,
646
	.sleepdep_srcs	= gfx_sgx_sleepdeps,
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	.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
};

static struct clockdomain sgx_clkdm = {
	.name		= "sgx_clkdm",
653
	.pwrdm		= { .name = "sgx_pwrdm" },
654
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
655
	.wkdep_srcs	= gfx_sgx_wkdeps,
656
	.sleepdep_srcs	= gfx_sgx_sleepdeps,
657
	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
658
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
659 660
};

661 662 663 664 665 666 667
/*
 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
 * then that information was removed from the 34xx ES2+ TRM.  It is
 * unclear whether the core is still there, but the clockdomain logic
 * is there, and must be programmed to an appropriate state if the
 * CORE clockdomain is to become inactive.
 */
668 669
static struct clockdomain d2d_clkdm = {
	.name		= "d2d_clkdm",
670
	.pwrdm		= { .name = "core_pwrdm" },
671
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
672
	.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
673
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
674 675
};

676 677
/*
 * XXX add usecounting for clkdm dependencies, otherwise the presence
678
 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
679 680
 * could cause trouble
 */
681
static struct clockdomain core_l3_3xxx_clkdm = {
682
	.name		= "core_l3_clkdm",
683
	.pwrdm		= { .name = "core_pwrdm" },
684
	.flags		= CLKDM_CAN_HWSUP,
685
	.dep_bit	= OMAP3430_EN_CORE_SHIFT,
686 687 688 689
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

690 691
/*
 * XXX add usecounting for clkdm dependencies, otherwise the presence
692
 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
693 694
 * could cause trouble
 */
695
static struct clockdomain core_l4_3xxx_clkdm = {
696
	.name		= "core_l4_clkdm",
697
	.pwrdm		= { .name = "core_pwrdm" },
698
	.flags		= CLKDM_CAN_HWSUP,
699
	.dep_bit	= OMAP3430_EN_CORE_SHIFT,
700 701 702 703
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

704
/* Another case of bit name collisions between several registers: EN_DSS */
705
static struct clockdomain dss_3xxx_clkdm = {
706
	.name		= "dss_clkdm",
707
	.pwrdm		= { .name = "dss_pwrdm" },
708
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
709
	.dep_bit	= OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
710 711
	.wkdep_srcs	= dss_wkdeps,
	.sleepdep_srcs	= dss_sleepdeps,
712 713 714 715 716 717
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain cam_clkdm = {
	.name		= "cam_clkdm",
718
	.pwrdm		= { .name = "cam_pwrdm" },
719
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
720 721
	.wkdep_srcs	= cam_wkdeps,
	.sleepdep_srcs	= cam_sleepdeps,
722 723 724 725 726 727
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain usbhost_clkdm = {
	.name		= "usbhost_clkdm",
728
	.pwrdm		= { .name = "usbhost_pwrdm" },
729
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
730 731
	.wkdep_srcs	= usbhost_wkdeps,
	.sleepdep_srcs	= usbhost_sleepdeps,
732
	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
733
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
734 735 736 737
};

static struct clockdomain per_clkdm = {
	.name		= "per_clkdm",
738
	.pwrdm		= { .name = "per_pwrdm" },
739
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
740
	.dep_bit	= OMAP3430_EN_PER_SHIFT,
741 742
	.wkdep_srcs	= per_wkdeps,
	.sleepdep_srcs	= per_sleepdeps,
743 744 745 746
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

747 748 749 750
/*
 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
 * switched of even if sdti is in use
 */
751 752
static struct clockdomain emu_clkdm = {
	.name		= "emu_clkdm",
753
	.pwrdm		= { .name = "emu_pwrdm" },
754
	.flags		= /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
755 756 757 758
	.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785
static struct clockdomain dpll1_clkdm = {
	.name		= "dpll1_clkdm",
	.pwrdm		= { .name = "dpll1_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll2_clkdm = {
	.name		= "dpll2_clkdm",
	.pwrdm		= { .name = "dpll2_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll3_clkdm = {
	.name		= "dpll3_clkdm",
	.pwrdm		= { .name = "dpll3_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll4_clkdm = {
	.name		= "dpll4_clkdm",
	.pwrdm		= { .name = "dpll4_pwrdm" },
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct clockdomain dpll5_clkdm = {
	.name		= "dpll5_clkdm",
	.pwrdm		= { .name = "dpll5_pwrdm" },
786
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
787 788
};

789
#endif   /* CONFIG_ARCH_OMAP3 */
790 791

/*
792
 * Clockdomain hwsup dependencies (OMAP3 only)
793 794
 */

795
static struct clkdm_autodep clkdm_autodeps[] = {
796
	{
797
		.clkdm	   = { .name = "mpu_clkdm" },
798 799 800
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
	{
801
		.clkdm	   = { .name = "iva2_clkdm" },
802 803
		.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
	},
804
	{
805
		.clkdm	   = { .name = NULL },
806
	}
807 808
};

809
static struct clockdomain *clockdomains_omap2[] __initdata = {
810
	&wkup_clkdm,
811 812
	&cm_clkdm,
	&prm_clkdm,
813

814
#ifdef CONFIG_SOC_OMAP2420
815 816
	&mpu_2420_clkdm,
	&iva1_2420_clkdm,
817 818 819 820 821
	&dsp_2420_clkdm,
	&gfx_2420_clkdm,
	&core_l3_2420_clkdm,
	&core_l4_2420_clkdm,
	&dss_2420_clkdm,
822 823
#endif

824
#ifdef CONFIG_SOC_OMAP2430
825 826
	&mpu_2430_clkdm,
	&mdm_clkdm,
827 828 829 830 831
	&dsp_2430_clkdm,
	&gfx_2430_clkdm,
	&core_l3_2430_clkdm,
	&core_l4_2430_clkdm,
	&dss_2430_clkdm,
832 833
#endif

834 835
#ifdef CONFIG_ARCH_OMAP3
	&mpu_3xxx_clkdm,
836 837 838 839 840
	&neon_clkdm,
	&iva2_clkdm,
	&gfx_3430es1_clkdm,
	&sgx_clkdm,
	&d2d_clkdm,
841 842 843
	&core_l3_3xxx_clkdm,
	&core_l4_3xxx_clkdm,
	&dss_3xxx_clkdm,
844 845 846 847
	&cam_clkdm,
	&usbhost_clkdm,
	&per_clkdm,
	&emu_clkdm,
848 849 850 851 852
	&dpll1_clkdm,
	&dpll2_clkdm,
	&dpll3_clkdm,
	&dpll4_clkdm,
	&dpll5_clkdm,
853 854 855 856
#endif
	NULL,
};

857 858 859 860
void __init omap2_clockdomains_init(void)
{
	clkdm_init(clockdomains_omap2, clkdm_autodeps);
}