imx290.c 35.8 KB
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// SPDX-License-Identifier: GPL-2.0
/*
 * Sony IMX290 CMOS Image Sensor Driver
 *
 * Copyright (C) 2019 FRAMOS GmbH.
 *
 * Copyright (C) 2019 Linaro Ltd.
 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <media/media-entity.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>

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#define IMX290_REG_SIZE_SHIFT				16
#define IMX290_REG_ADDR_MASK				0xffff
#define IMX290_REG_8BIT(n)				((1U << IMX290_REG_SIZE_SHIFT) | (n))
#define IMX290_REG_16BIT(n)				((2U << IMX290_REG_SIZE_SHIFT) | (n))
#define IMX290_REG_24BIT(n)				((3U << IMX290_REG_SIZE_SHIFT) | (n))

#define IMX290_STANDBY					IMX290_REG_8BIT(0x3000)
#define IMX290_REGHOLD					IMX290_REG_8BIT(0x3001)
#define IMX290_XMSTA					IMX290_REG_8BIT(0x3002)
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#define IMX290_ADBIT					IMX290_REG_8BIT(0x3005)
#define IMX290_ADBIT_10BIT				(0 << 0)
#define IMX290_ADBIT_12BIT				(1 << 0)
#define IMX290_CTRL_07					IMX290_REG_8BIT(0x3007)
#define IMX290_VREVERSE					BIT(0)
#define IMX290_HREVERSE					BIT(1)
#define IMX290_WINMODE_1080P				(0 << 4)
#define IMX290_WINMODE_720P				(1 << 4)
#define IMX290_WINMODE_CROP				(4 << 4)
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#define IMX290_FR_FDG_SEL				IMX290_REG_8BIT(0x3009)
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#define IMX290_BLKLEVEL					IMX290_REG_16BIT(0x300a)
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#define IMX290_GAIN					IMX290_REG_8BIT(0x3014)
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#define IMX290_VMAX					IMX290_REG_24BIT(0x3018)
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#define IMX290_HMAX					IMX290_REG_16BIT(0x301c)
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#define IMX290_SHS1					IMX290_REG_24BIT(0x3020)
#define IMX290_WINWV_OB					IMX290_REG_8BIT(0x303a)
#define IMX290_WINPV					IMX290_REG_16BIT(0x303c)
#define IMX290_WINWV					IMX290_REG_16BIT(0x303e)
#define IMX290_WINPH					IMX290_REG_16BIT(0x3040)
#define IMX290_WINWH					IMX290_REG_16BIT(0x3042)
#define IMX290_OUT_CTRL					IMX290_REG_8BIT(0x3046)
#define IMX290_ODBIT_10BIT				(0 << 0)
#define IMX290_ODBIT_12BIT				(1 << 0)
#define IMX290_OPORTSEL_PARALLEL			(0x0 << 4)
#define IMX290_OPORTSEL_LVDS_2CH			(0xd << 4)
#define IMX290_OPORTSEL_LVDS_4CH			(0xe << 4)
#define IMX290_OPORTSEL_LVDS_8CH			(0xf << 4)
#define IMX290_XSOUTSEL					IMX290_REG_8BIT(0x304b)
#define IMX290_XSOUTSEL_XVSOUTSEL_HIGH			(0 << 0)
#define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC			(2 << 0)
#define IMX290_XSOUTSEL_XHSOUTSEL_HIGH			(0 << 2)
#define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC			(2 << 2)
#define IMX290_INCKSEL1					IMX290_REG_8BIT(0x305c)
#define IMX290_INCKSEL2					IMX290_REG_8BIT(0x305d)
#define IMX290_INCKSEL3					IMX290_REG_8BIT(0x305e)
#define IMX290_INCKSEL4					IMX290_REG_8BIT(0x305f)
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#define IMX290_PGCTRL					IMX290_REG_8BIT(0x308c)
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#define IMX290_ADBIT1					IMX290_REG_8BIT(0x3129)
#define IMX290_ADBIT1_10BIT				0x1d
#define IMX290_ADBIT1_12BIT				0x00
#define IMX290_INCKSEL5					IMX290_REG_8BIT(0x315e)
#define IMX290_INCKSEL6					IMX290_REG_8BIT(0x3164)
#define IMX290_ADBIT2					IMX290_REG_8BIT(0x317c)
#define IMX290_ADBIT2_10BIT				0x12
#define IMX290_ADBIT2_12BIT				0x00
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#define IMX290_CHIP_ID					IMX290_REG_16BIT(0x319a)
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#define IMX290_ADBIT3					IMX290_REG_8BIT(0x31ec)
#define IMX290_ADBIT3_10BIT				0x37
#define IMX290_ADBIT3_12BIT				0x0e
#define IMX290_REPETITION				IMX290_REG_8BIT(0x3405)
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#define IMX290_PHY_LANE_NUM				IMX290_REG_8BIT(0x3407)
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#define IMX290_OPB_SIZE_V				IMX290_REG_8BIT(0x3414)
#define IMX290_Y_OUT_SIZE				IMX290_REG_16BIT(0x3418)
#define IMX290_CSI_DT_FMT				IMX290_REG_16BIT(0x3441)
#define IMX290_CSI_DT_FMT_RAW10				0x0a0a
#define IMX290_CSI_DT_FMT_RAW12				0x0c0c
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#define IMX290_CSI_LANE_MODE				IMX290_REG_8BIT(0x3443)
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#define IMX290_EXTCK_FREQ				IMX290_REG_16BIT(0x3444)
#define IMX290_TCLKPOST					IMX290_REG_16BIT(0x3446)
#define IMX290_THSZERO					IMX290_REG_16BIT(0x3448)
#define IMX290_THSPREPARE				IMX290_REG_16BIT(0x344a)
#define IMX290_TCLKTRAIL				IMX290_REG_16BIT(0x344c)
#define IMX290_THSTRAIL					IMX290_REG_16BIT(0x344e)
#define IMX290_TCLKZERO					IMX290_REG_16BIT(0x3450)
#define IMX290_TCLKPREPARE				IMX290_REG_16BIT(0x3452)
#define IMX290_TLPX					IMX290_REG_16BIT(0x3454)
#define IMX290_X_OUT_SIZE				IMX290_REG_16BIT(0x3472)
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#define IMX290_PGCTRL_REGEN				BIT(0)
#define IMX290_PGCTRL_THRU				BIT(1)
#define IMX290_PGCTRL_MODE(n)				((n) << 4)
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#define IMX290_VMAX_DEFAULT				1125

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/*
 * The IMX290 pixel array is organized as follows:
 *
 *     +------------------------------------+
 *     |           Optical Black            |     }  Vertical effective optical black (10)
 * +---+------------------------------------+---+
 * |   |                                    |   | }  Effective top margin (8)
 * |   |   +----------------------------+   |   | \
 * |   |   |                            |   |   |  |
 * |   |   |                            |   |   |  |
 * |   |   |                            |   |   |  |
 * |   |   |    Recording Pixel Area    |   |   |  | Recommended height (1080)
 * |   |   |                            |   |   |  |
 * |   |   |                            |   |   |  |
 * |   |   |                            |   |   |  |
 * |   |   +----------------------------+   |   | /
 * |   |                                    |   | }  Effective bottom margin (9)
 * +---+------------------------------------+---+
 *  <-> <-> <--------------------------> <-> <->
 *                                            \----  Ignored right margin (4)
 *                                        \--------  Effective right margin (9)
 *                       \-------------------------  Recommended width (1920)
 *       \-----------------------------------------  Effective left margin (8)
 *   \---------------------------------------------  Ignored left margin (4)
 *
 * The optical black lines are output over CSI-2 with a separate data type.
 *
 * The pixel array is meant to have 1920x1080 usable pixels after image
 * processing in an ISP. It has 8 (9) extra active pixels usable for color
 * processing in the ISP on the top and left (bottom and right) sides of the
 * image. In addition, 4 additional pixels are present on the left and right
 * sides of the image, documented as "ignored area".
 *
 * As far as is understood, all pixels of the pixel array (ignored area, color
 * processing margins and recording area) can be output by the sensor.
 */

#define IMX290_PIXEL_ARRAY_WIDTH			1945
#define IMX290_PIXEL_ARRAY_HEIGHT			1097
#define IMX920_PIXEL_ARRAY_MARGIN_LEFT			12
#define IMX920_PIXEL_ARRAY_MARGIN_RIGHT			13
#define IMX920_PIXEL_ARRAY_MARGIN_TOP			8
#define IMX920_PIXEL_ARRAY_MARGIN_BOTTOM		9
#define IMX290_PIXEL_ARRAY_RECORDING_WIDTH		1920
#define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT		1080

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/* Equivalent value for 16bpp */
#define IMX290_BLACK_LEVEL_DEFAULT			3840

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#define IMX290_NUM_SUPPLIES				3
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struct imx290_regval {
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	u32 reg;
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	u32 val;
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};

struct imx290_mode {
	u32 width;
	u32 height;
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	u32 hmax;
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	u8 link_freq_index;
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	const struct imx290_regval *data;
	u32 data_size;
};

struct imx290 {
	struct device *dev;
	struct clk *xclk;
	struct regmap *regmap;
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	u8 nlanes;
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	struct v4l2_subdev sd;
	struct media_pad pad;
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	const struct imx290_mode *current_mode;
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	u8 bpp;
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	struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES];
	struct gpio_desc *rst_gpio;

	struct v4l2_ctrl_handler ctrls;
	struct v4l2_ctrl *link_freq;
	struct v4l2_ctrl *pixel_rate;
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	struct v4l2_ctrl *hblank;
	struct v4l2_ctrl *vblank;
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};

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static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
{
	return container_of(_sd, struct imx290, sd);
}
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/* -----------------------------------------------------------------------------
 * Modes and formats
 */
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static const struct imx290_regval imx290_global_init_settings[] = {
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	{ IMX290_CTRL_07, IMX290_WINMODE_1080P },
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	{ IMX290_VMAX, IMX290_VMAX_DEFAULT },
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	{ IMX290_EXTCK_FREQ, 0x2520 },
	{ IMX290_WINWV_OB, 12 },
	{ IMX290_WINPH, 0 },
	{ IMX290_WINPV, 0 },
	{ IMX290_WINWH, 1948 },
	{ IMX290_WINWV, 1097 },
	{ IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC |
			   IMX290_XSOUTSEL_XHSOUTSEL_HSYNC },
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	{ IMX290_REG_8BIT(0x300f), 0x00 },
	{ IMX290_REG_8BIT(0x3010), 0x21 },
	{ IMX290_REG_8BIT(0x3012), 0x64 },
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	{ IMX290_REG_8BIT(0x3013), 0x00 },
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	{ IMX290_REG_8BIT(0x3016), 0x09 },
	{ IMX290_REG_8BIT(0x3070), 0x02 },
	{ IMX290_REG_8BIT(0x3071), 0x11 },
	{ IMX290_REG_8BIT(0x309b), 0x10 },
	{ IMX290_REG_8BIT(0x309c), 0x22 },
	{ IMX290_REG_8BIT(0x30a2), 0x02 },
	{ IMX290_REG_8BIT(0x30a6), 0x20 },
	{ IMX290_REG_8BIT(0x30a8), 0x20 },
	{ IMX290_REG_8BIT(0x30aa), 0x20 },
	{ IMX290_REG_8BIT(0x30ac), 0x20 },
	{ IMX290_REG_8BIT(0x30b0), 0x43 },
	{ IMX290_REG_8BIT(0x3119), 0x9e },
	{ IMX290_REG_8BIT(0x311c), 0x1e },
	{ IMX290_REG_8BIT(0x311e), 0x08 },
	{ IMX290_REG_8BIT(0x3128), 0x05 },
	{ IMX290_REG_8BIT(0x313d), 0x83 },
	{ IMX290_REG_8BIT(0x3150), 0x03 },
	{ IMX290_REG_8BIT(0x317e), 0x00 },
	{ IMX290_REG_8BIT(0x32b8), 0x50 },
	{ IMX290_REG_8BIT(0x32b9), 0x10 },
	{ IMX290_REG_8BIT(0x32ba), 0x00 },
	{ IMX290_REG_8BIT(0x32bb), 0x04 },
	{ IMX290_REG_8BIT(0x32c8), 0x50 },
	{ IMX290_REG_8BIT(0x32c9), 0x10 },
	{ IMX290_REG_8BIT(0x32ca), 0x00 },
	{ IMX290_REG_8BIT(0x32cb), 0x04 },
	{ IMX290_REG_8BIT(0x332c), 0xd3 },
	{ IMX290_REG_8BIT(0x332d), 0x10 },
	{ IMX290_REG_8BIT(0x332e), 0x0d },
	{ IMX290_REG_8BIT(0x3358), 0x06 },
	{ IMX290_REG_8BIT(0x3359), 0xe1 },
	{ IMX290_REG_8BIT(0x335a), 0x11 },
	{ IMX290_REG_8BIT(0x3360), 0x1e },
	{ IMX290_REG_8BIT(0x3361), 0x61 },
	{ IMX290_REG_8BIT(0x3362), 0x10 },
	{ IMX290_REG_8BIT(0x33b0), 0x50 },
	{ IMX290_REG_8BIT(0x33b2), 0x1a },
	{ IMX290_REG_8BIT(0x33b3), 0x04 },
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	{ IMX290_REG_8BIT(0x3480), 0x49 },
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};

static const struct imx290_regval imx290_1080p_settings[] = {
	/* mode settings */
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	{ IMX290_CTRL_07, IMX290_WINMODE_1080P },
	{ IMX290_WINWV_OB, 12 },
	{ IMX290_OPB_SIZE_V, 10 },
	{ IMX290_X_OUT_SIZE, 1920 },
	{ IMX290_Y_OUT_SIZE, 1080 },
	{ IMX290_INCKSEL1, 0x18 },
	{ IMX290_INCKSEL2, 0x03 },
	{ IMX290_INCKSEL3, 0x20 },
	{ IMX290_INCKSEL4, 0x01 },
	{ IMX290_INCKSEL5, 0x1a },
	{ IMX290_INCKSEL6, 0x1a },
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	/* data rate settings */
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	{ IMX290_REPETITION, 0x10 },
	{ IMX290_TCLKPOST, 87 },
	{ IMX290_THSZERO, 55 },
	{ IMX290_THSPREPARE, 31 },
	{ IMX290_TCLKTRAIL, 31 },
	{ IMX290_THSTRAIL, 31 },
	{ IMX290_TCLKZERO, 119 },
	{ IMX290_TCLKPREPARE, 31 },
	{ IMX290_TLPX, 23 },
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};

static const struct imx290_regval imx290_720p_settings[] = {
	/* mode settings */
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	{ IMX290_CTRL_07, IMX290_WINMODE_720P },
	{ IMX290_WINWV_OB, 6 },
	{ IMX290_OPB_SIZE_V, 4 },
	{ IMX290_X_OUT_SIZE, 1280 },
	{ IMX290_Y_OUT_SIZE, 720 },
	{ IMX290_INCKSEL1, 0x20 },
	{ IMX290_INCKSEL2, 0x00 },
	{ IMX290_INCKSEL3, 0x20 },
	{ IMX290_INCKSEL4, 0x01 },
	{ IMX290_INCKSEL5, 0x1a },
	{ IMX290_INCKSEL6, 0x1a },
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	/* data rate settings */
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	{ IMX290_REPETITION, 0x10 },
	{ IMX290_TCLKPOST, 79 },
	{ IMX290_THSZERO, 47 },
	{ IMX290_THSPREPARE, 23 },
	{ IMX290_TCLKTRAIL, 23 },
	{ IMX290_THSTRAIL, 23 },
	{ IMX290_TCLKZERO, 87 },
	{ IMX290_TCLKPREPARE, 23 },
	{ IMX290_TLPX, 23 },
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};

static const struct imx290_regval imx290_10bit_settings[] = {
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	{ IMX290_ADBIT, IMX290_ADBIT_10BIT },
	{ IMX290_OUT_CTRL, IMX290_ODBIT_10BIT },
	{ IMX290_ADBIT1, IMX290_ADBIT1_10BIT },
	{ IMX290_ADBIT2, IMX290_ADBIT2_10BIT },
	{ IMX290_ADBIT3, IMX290_ADBIT3_10BIT },
	{ IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 },
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};

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static const struct imx290_regval imx290_12bit_settings[] = {
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	{ IMX290_ADBIT, IMX290_ADBIT_12BIT },
	{ IMX290_OUT_CTRL, IMX290_ODBIT_12BIT },
	{ IMX290_ADBIT1, IMX290_ADBIT1_12BIT },
	{ IMX290_ADBIT2, IMX290_ADBIT2_12BIT },
	{ IMX290_ADBIT3, IMX290_ADBIT3_12BIT },
	{ IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 },
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};

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/* supported link frequencies */
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#define FREQ_INDEX_1080P	0
#define FREQ_INDEX_720P		1
static const s64 imx290_link_freq_2lanes[] = {
	[FREQ_INDEX_1080P] = 445500000,
	[FREQ_INDEX_720P] = 297000000,
};
static const s64 imx290_link_freq_4lanes[] = {
	[FREQ_INDEX_1080P] = 222750000,
	[FREQ_INDEX_720P] = 148500000,
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};

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/*
 * In this function and in the similar ones below We rely on imx290_probe()
 * to ensure that nlanes is either 2 or 4.
 */
static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290)
{
	if (imx290->nlanes == 2)
		return imx290_link_freq_2lanes;
	else
		return imx290_link_freq_4lanes;
}

static inline int imx290_link_freqs_num(const struct imx290 *imx290)
{
	if (imx290->nlanes == 2)
		return ARRAY_SIZE(imx290_link_freq_2lanes);
	else
		return ARRAY_SIZE(imx290_link_freq_4lanes);
}

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/* Mode configs */
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static const struct imx290_mode imx290_modes_2lanes[] = {
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	{
		.width = 1920,
		.height = 1080,
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		.hmax = 4400,
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		.link_freq_index = FREQ_INDEX_1080P,
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		.data = imx290_1080p_settings,
		.data_size = ARRAY_SIZE(imx290_1080p_settings),
	},
	{
		.width = 1280,
		.height = 720,
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		.hmax = 6600,
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		.link_freq_index = FREQ_INDEX_720P,
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		.data = imx290_720p_settings,
		.data_size = ARRAY_SIZE(imx290_720p_settings),
	},
};

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static const struct imx290_mode imx290_modes_4lanes[] = {
	{
		.width = 1920,
		.height = 1080,
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		.hmax = 2200,
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		.link_freq_index = FREQ_INDEX_1080P,
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		.data = imx290_1080p_settings,
		.data_size = ARRAY_SIZE(imx290_1080p_settings),
	},
	{
		.width = 1280,
		.height = 720,
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		.hmax = 3300,
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		.link_freq_index = FREQ_INDEX_720P,
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		.data = imx290_720p_settings,
		.data_size = ARRAY_SIZE(imx290_720p_settings),
	},
};

static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290)
{
	if (imx290->nlanes == 2)
		return imx290_modes_2lanes;
	else
		return imx290_modes_4lanes;
}

static inline int imx290_modes_num(const struct imx290 *imx290)
{
	if (imx290->nlanes == 2)
		return ARRAY_SIZE(imx290_modes_2lanes);
	else
		return ARRAY_SIZE(imx290_modes_4lanes);
}

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struct imx290_pixfmt {
	u32 code;
	u8 bpp;
};

static const struct imx290_pixfmt imx290_formats[] = {
	{ MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
	{ MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
};

/* -----------------------------------------------------------------------------
 * Register access
 */
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static int __always_unused imx290_read(struct imx290 *imx290, u32 addr, u32 *value)
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{
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	u8 data[3] = { 0, 0, 0 };
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	int ret;

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	ret = regmap_raw_read(imx290->regmap, addr & IMX290_REG_ADDR_MASK,
			      data, (addr >> IMX290_REG_SIZE_SHIFT) & 3);
	if (ret < 0) {
		dev_err(imx290->dev, "%u-bit read from 0x%04x failed: %d\n",
			 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8,
			 addr & IMX290_REG_ADDR_MASK, ret);
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		return ret;
	}

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	*value = (data[2] << 16) | (data[1] << 8) | data[0];
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	return 0;
}

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static int imx290_write(struct imx290 *imx290, u32 addr, u32 value, int *err)
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{
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	u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 };
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	int ret;

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	if (err && *err)
		return *err;

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	ret = regmap_raw_write(imx290->regmap, addr & IMX290_REG_ADDR_MASK,
			       data, (addr >> IMX290_REG_SIZE_SHIFT) & 3);
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	if (ret < 0) {
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		dev_err(imx290->dev, "%u-bit write to 0x%04x failed: %d\n",
			 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8,
			 addr & IMX290_REG_ADDR_MASK, ret);
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		if (err)
			*err = ret;
	}
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	return ret;
}

static int imx290_set_register_array(struct imx290 *imx290,
				     const struct imx290_regval *settings,
				     unsigned int num_settings)
{
	unsigned int i;
	int ret;

	for (i = 0; i < num_settings; ++i, ++settings) {
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		ret = imx290_write(imx290, settings->reg, settings->val, NULL);
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		if (ret < 0)
			return ret;
	}

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	/* Provide 10ms settle time */
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	usleep_range(10000, 11000);
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	return 0;
}

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static int imx290_set_data_lanes(struct imx290 *imx290)
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{
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	int ret = 0, laneval, frsel;
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	switch (imx290->nlanes) {
	case 2:
		laneval = 0x01;
		frsel = 0x02;
		break;
	case 4:
		laneval = 0x03;
		frsel = 0x01;
		break;
	default:
		/*
		 * We should never hit this since the data lane count is
		 * validated in probe itself
		 */
		dev_err(imx290->dev, "Lane configuration not supported\n");
		return -EINVAL;
	}
510

511 512 513
	imx290_write(imx290, IMX290_PHY_LANE_NUM, laneval, &ret);
	imx290_write(imx290, IMX290_CSI_LANE_MODE, laneval, &ret);
	imx290_write(imx290, IMX290_FR_FDG_SEL, frsel, &ret);
514

515 516 517
	return ret;
}

518 519 520 521 522 523 524
static int imx290_set_black_level(struct imx290 *imx290,
				  unsigned int black_level, int *err)
{
	return imx290_write(imx290, IMX290_BLKLEVEL,
			    black_level >> (16 - imx290->bpp), err);
}

525 526
static int imx290_setup_format(struct imx290 *imx290,
			       const struct v4l2_mbus_framefmt *format)
527
{
528 529
	const struct imx290_regval *regs;
	unsigned int num_regs;
530 531
	int ret;

532
	switch (format->code) {
533
	case MEDIA_BUS_FMT_SRGGB10_1X10:
534 535
		regs = imx290_10bit_settings;
		num_regs = ARRAY_SIZE(imx290_10bit_settings);
536 537
		break;
	case MEDIA_BUS_FMT_SRGGB12_1X12:
538 539
		regs = imx290_12bit_settings;
		num_regs = ARRAY_SIZE(imx290_12bit_settings);
540 541 542 543 544 545
		break;
	default:
		dev_err(imx290->dev, "Unknown pixel format\n");
		return -EINVAL;
	}

546 547 548 549 550 551 552
	ret = imx290_set_register_array(imx290, regs, num_regs);
	if (ret < 0) {
		dev_err(imx290->dev, "Could not set format registers\n");
		return ret;
	}

	return imx290_set_black_level(imx290, IMX290_BLACK_LEVEL_DEFAULT, &ret);
553 554 555 556 557 558
}

/* ----------------------------------------------------------------------------
 * Controls
 */

559 560 561 562 563 564
static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)
{
	struct imx290 *imx290 = container_of(ctrl->handler,
					     struct imx290, ctrls);
	int ret = 0;

565 566 567 568 569 570 571 572 573
	/*
	 * Return immediately for controls that don't need to be applied to the
	 * device. Those controls are modified in imx290_ctrl_update(), which
	 * is called at probe time before runtime PM is initialized, so we
	 * can't proceed to the pm_runtime_get_if_in_use() call below.
	 */
	if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY)
		return 0;

574 575 576 577 578
	/* V4L2 controls values will be applied only when power is already up */
	if (!pm_runtime_get_if_in_use(imx290->dev))
		return 0;

	switch (ctrl->id) {
579
	case V4L2_CID_ANALOGUE_GAIN:
580
		ret = imx290_write(imx290, IMX290_GAIN, ctrl->val, NULL);
581
		break;
582 583 584 585 586 587

	case V4L2_CID_EXPOSURE:
		ret = imx290_write(imx290, IMX290_SHS1,
				   IMX290_VMAX_DEFAULT - ctrl->val - 1, NULL);
		break;

588 589
	case V4L2_CID_TEST_PATTERN:
		if (ctrl->val) {
590
			imx290_set_black_level(imx290, 0, &ret);
591
			usleep_range(10000, 11000);
592 593 594 595
			imx290_write(imx290, IMX290_PGCTRL,
				     (u8)(IMX290_PGCTRL_REGEN |
				     IMX290_PGCTRL_THRU |
				     IMX290_PGCTRL_MODE(ctrl->val)), &ret);
596
		} else {
597
			imx290_write(imx290, IMX290_PGCTRL, 0x00, &ret);
598
			usleep_range(10000, 11000);
599 600
			imx290_set_black_level(imx290, IMX290_BLACK_LEVEL_DEFAULT,
					       &ret);
601 602
		}
		break;
603

604 605 606 607 608 609 610 611 612 613 614 615 616 617
	default:
		ret = -EINVAL;
		break;
	}

	pm_runtime_put(imx290->dev);

	return ret;
}

static const struct v4l2_ctrl_ops imx290_ctrl_ops = {
	.s_ctrl = imx290_set_ctrl,
};

618 619 620 621 622 623 624 625 626 627
static const char * const imx290_test_pattern_menu[] = {
	"Disabled",
	"Sequence Pattern 1",
	"Horizontal Color-bar Chart",
	"Vertical Color-bar Chart",
	"Sequence Pattern 2",
	"Gradation Pattern 1",
	"Gradation Pattern 2",
	"000/555h Toggle Pattern",
};
628

629 630 631 632 633
static void imx290_ctrl_update(struct imx290 *imx290,
			       const struct imx290_mode *mode)
{
	unsigned int hblank = mode->hmax - mode->width;
	unsigned int vblank = IMX290_VMAX_DEFAULT - mode->height;
634 635
	s64 link_freq = imx290_link_freqs_ptr(imx290)[mode->link_freq_index];
	u64 pixel_rate;
636

637 638 639 640
	/* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
	pixel_rate = link_freq * 2 * imx290->nlanes;
	do_div(pixel_rate, imx290->bpp);

641
	__v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index);
642
	__v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate, pixel_rate);
643 644 645 646 647

	__v4l2_ctrl_modify_range(imx290->hblank, hblank, hblank, 1, hblank);
	__v4l2_ctrl_modify_range(imx290->vblank, vblank, vblank, 1, vblank);
}

648
static int imx290_ctrl_init(struct imx290 *imx290)
649
{
650 651
	struct v4l2_fwnode_device_properties props;
	int ret;
652

653 654 655
	ret = v4l2_fwnode_device_parse(imx290->dev, &props);
	if (ret < 0)
		return ret;
656

657
	v4l2_ctrl_handler_init(&imx290->ctrls, 9);
658

659 660 661 662 663 664 665 666 667 668 669 670 671 672 673
	/*
	 * The sensor has an analog gain and a digital gain, both controlled
	 * through a single gain value, expressed in 0.3dB increments. Values
	 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values
	 * up to 72.0dB (240) add further digital gain. Limit the range to
	 * analog gain only, support for digital gain can be added separately
	 * if needed.
	 *
	 * The IMX327 and IMX462 are largely compatible with the IMX290, but
	 * have an analog gain range of 0.0dB to 29.4dB and 42dB of digital
	 * gain. When support for those sensors gets added to the driver, the
	 * gain control should be adjusted accordingly.
	 */
	v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
			  V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0);
674

675 676 677
	v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
			  V4L2_CID_EXPOSURE, 1, IMX290_VMAX_DEFAULT - 2, 1,
			  IMX290_VMAX_DEFAULT - 2);
678

679 680 681 682 683
	/*
	 * Set the link frequency, pixel rate, horizontal blanking and vertical
	 * blanking to hardcoded values, they will be updated by
	 * imx290_ctrl_update().
	 */
684 685 686 687 688 689 690
	imx290->link_freq =
		v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,
				       V4L2_CID_LINK_FREQ,
				       imx290_link_freqs_num(imx290) - 1, 0,
				       imx290_link_freqs_ptr(imx290));
	if (imx290->link_freq)
		imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
691

692 693
	imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
					       V4L2_CID_PIXEL_RATE,
694
					       1, INT_MAX, 1, 1);
695

696 697 698 699
	v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops,
				     V4L2_CID_TEST_PATTERN,
				     ARRAY_SIZE(imx290_test_pattern_menu) - 1,
				     0, 0, imx290_test_pattern_menu);
700

701
	imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
702
					   V4L2_CID_HBLANK, 1, 1, 1, 1);
703 704
	if (imx290->hblank)
		imx290->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
705

706
	imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
707
					   V4L2_CID_VBLANK, 1, 1, 1, 1);
708 709
	if (imx290->vblank)
		imx290->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
710

711 712
	v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops,
					&props);
713

714 715 716 717 718 719 720
	imx290->sd.ctrl_handler = &imx290->ctrls;

	if (imx290->ctrls.error) {
		ret = imx290->ctrls.error;
		v4l2_ctrl_handler_free(&imx290->ctrls);
		return ret;
	}
721 722 723 724

	return 0;
}

725 726 727
/* ----------------------------------------------------------------------------
 * Subdev operations
 */
728

729
/* Start streaming */
730 731
static int imx290_start_streaming(struct imx290 *imx290,
				  struct v4l2_subdev_state *state)
732
{
733
	const struct v4l2_mbus_framefmt *format;
734
	int ret;
735

736 737 738 739 740 741 742 743 744 745
	/* Set init register settings */
	ret = imx290_set_register_array(imx290, imx290_global_init_settings,
					ARRAY_SIZE(
						imx290_global_init_settings));
	if (ret < 0) {
		dev_err(imx290->dev, "Could not set init registers\n");
		return ret;
	}

	/* Apply the register values related to current frame format */
746 747
	format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0);
	ret = imx290_setup_format(imx290, format);
748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766
	if (ret < 0) {
		dev_err(imx290->dev, "Could not set frame format\n");
		return ret;
	}

	/* Apply default values of current mode */
	ret = imx290_set_register_array(imx290, imx290->current_mode->data,
					imx290->current_mode->data_size);
	if (ret < 0) {
		dev_err(imx290->dev, "Could not set current mode\n");
		return ret;
	}

	ret = imx290_write(imx290, IMX290_HMAX, imx290->current_mode->hmax,
			   NULL);
	if (ret)
		return ret;

	/* Apply customized values from user */
767
	ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler);
768 769 770 771 772 773 774 775 776 777 778
	if (ret) {
		dev_err(imx290->dev, "Could not sync v4l2 controls\n");
		return ret;
	}

	imx290_write(imx290, IMX290_STANDBY, 0x00, &ret);

	msleep(30);

	/* Start streaming */
	return imx290_write(imx290, IMX290_XMSTA, 0x00, &ret);
779 780
}

781 782
/* Stop streaming */
static int imx290_stop_streaming(struct imx290 *imx290)
783
{
784
	int ret = 0;
785

786 787 788 789 790 791 792 793 794 795
	imx290_write(imx290, IMX290_STANDBY, 0x01, &ret);

	msleep(30);

	return imx290_write(imx290, IMX290_XMSTA, 0x01, &ret);
}

static int imx290_set_stream(struct v4l2_subdev *sd, int enable)
{
	struct imx290 *imx290 = to_imx290(sd);
796
	struct v4l2_subdev_state *state;
797 798
	int ret = 0;

799 800
	state = v4l2_subdev_lock_and_get_active_state(sd);

801 802 803
	if (enable) {
		ret = pm_runtime_resume_and_get(imx290->dev);
		if (ret < 0)
804
			goto unlock;
805

806
		ret = imx290_start_streaming(imx290, state);
807 808 809
		if (ret) {
			dev_err(imx290->dev, "Start stream failed\n");
			pm_runtime_put(imx290->dev);
810
			goto unlock;
811 812 813 814 815 816
		}
	} else {
		imx290_stop_streaming(imx290);
		pm_runtime_put(imx290->dev);
	}

817 818
unlock:
	v4l2_subdev_unlock_state(state);
819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855
	return ret;
}

static int imx290_enum_mbus_code(struct v4l2_subdev *sd,
				 struct v4l2_subdev_state *sd_state,
				 struct v4l2_subdev_mbus_code_enum *code)
{
	if (code->index >= ARRAY_SIZE(imx290_formats))
		return -EINVAL;

	code->code = imx290_formats[code->index].code;

	return 0;
}

static int imx290_enum_frame_size(struct v4l2_subdev *sd,
				  struct v4l2_subdev_state *sd_state,
				  struct v4l2_subdev_frame_size_enum *fse)
{
	const struct imx290 *imx290 = to_imx290(sd);
	const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290);

	if ((fse->code != imx290_formats[0].code) &&
	    (fse->code != imx290_formats[1].code))
		return -EINVAL;

	if (fse->index >= imx290_modes_num(imx290))
		return -EINVAL;

	fse->min_width = imx290_modes[fse->index].width;
	fse->max_width = imx290_modes[fse->index].width;
	fse->min_height = imx290_modes[fse->index].height;
	fse->max_height = imx290_modes[fse->index].height;

	return 0;
}

856
static int imx290_set_fmt(struct v4l2_subdev *sd,
857 858
			  struct v4l2_subdev_state *sd_state,
			  struct v4l2_subdev_format *fmt)
859 860 861 862 863 864
{
	struct imx290 *imx290 = to_imx290(sd);
	const struct imx290_mode *mode;
	struct v4l2_mbus_framefmt *format;
	unsigned int i;

865 866
	mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290),
				      imx290_modes_num(imx290), width, height,
867 868 869 870 871 872 873 874 875 876 877 878 879 880 881
				      fmt->format.width, fmt->format.height);

	fmt->format.width = mode->width;
	fmt->format.height = mode->height;

	for (i = 0; i < ARRAY_SIZE(imx290_formats); i++)
		if (imx290_formats[i].code == fmt->format.code)
			break;

	if (i >= ARRAY_SIZE(imx290_formats))
		i = 0;

	fmt->format.code = imx290_formats[i].code;
	fmt->format.field = V4L2_FIELD_NONE;

882
	format = v4l2_subdev_get_pad_format(sd, sd_state, 0);
883 884

	if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
885
		imx290->current_mode = mode;
886
		imx290->bpp = imx290_formats[i].bpp;
887

888
		imx290_ctrl_update(imx290, mode);
889 890 891 892 893 894 895
	}

	*format = fmt->format;

	return 0;
}

896 897 898 899 900 901 902 903
static int imx290_get_selection(struct v4l2_subdev *sd,
				struct v4l2_subdev_state *sd_state,
				struct v4l2_subdev_selection *sel)
{
	struct v4l2_mbus_framefmt *format;

	switch (sel->target) {
	case V4L2_SEL_TGT_CROP: {
904
		format = v4l2_subdev_get_pad_format(sd, sd_state, 0);
905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937

		sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP
			   + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2;
		sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT
			    + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2;
		sel->r.width = format->width;
		sel->r.height = format->height;

		return 0;
	}

	case V4L2_SEL_TGT_NATIVE_SIZE:
	case V4L2_SEL_TGT_CROP_BOUNDS:
		sel->r.top = 0;
		sel->r.left = 0;
		sel->r.width = IMX290_PIXEL_ARRAY_WIDTH;
		sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT;

		return 0;

	case V4L2_SEL_TGT_CROP_DEFAULT:
		sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP;
		sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT;
		sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH;
		sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT;

		return 0;

	default:
		return -EINVAL;
	}
}

938
static int imx290_entity_init_cfg(struct v4l2_subdev *subdev,
939
				  struct v4l2_subdev_state *sd_state)
940
{
941 942 943 944 945 946 947
	struct v4l2_subdev_format fmt = {
		.which = V4L2_SUBDEV_FORMAT_TRY,
		.format = {
			.width = 1920,
			.height = 1080,
		},
	};
948

949
	imx290_set_fmt(subdev, sd_state, &fmt);
950 951 952 953

	return 0;
}

954 955 956
static const struct v4l2_subdev_video_ops imx290_video_ops = {
	.s_stream = imx290_set_stream,
};
957

958 959 960 961
static const struct v4l2_subdev_pad_ops imx290_pad_ops = {
	.init_cfg = imx290_entity_init_cfg,
	.enum_mbus_code = imx290_enum_mbus_code,
	.enum_frame_size = imx290_enum_frame_size,
962
	.get_fmt = v4l2_subdev_get_fmt,
963 964 965
	.set_fmt = imx290_set_fmt,
	.get_selection = imx290_get_selection,
};
966

967 968 969 970
static const struct v4l2_subdev_ops imx290_subdev_ops = {
	.video = &imx290_video_ops,
	.pad = &imx290_pad_ops,
};
971

972 973 974
static const struct media_entity_operations imx290_subdev_entity_ops = {
	.link_validate = v4l2_subdev_link_validate,
};
975

976 977 978 979 980
static int imx290_subdev_init(struct imx290 *imx290)
{
	struct i2c_client *client = to_i2c_client(imx290->dev);
	int ret;

981 982
	imx290->current_mode = &imx290_modes_ptr(imx290)[0];
	imx290->bpp = imx290_formats[0].bpp;
983 984 985 986 987 988 989 990 991 992 993 994 995 996

	v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops);
	imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
	imx290->sd.dev = imx290->dev;
	imx290->sd.entity.ops = &imx290_subdev_entity_ops;
	imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;

	imx290->pad.flags = MEDIA_PAD_FL_SOURCE;
	ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad);
	if (ret < 0) {
		dev_err(imx290->dev, "Could not register media entity\n");
		return ret;
	}

997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
	ret = imx290_ctrl_init(imx290);
	if (ret < 0) {
		dev_err(imx290->dev, "Control initialization error %d\n", ret);
		goto err_media;
	}

	imx290->sd.state_lock = imx290->ctrls.lock;

	ret = v4l2_subdev_init_finalize(&imx290->sd);
	if (ret < 0) {
		dev_err(imx290->dev, "subdev initialization error %d\n", ret);
		goto err_ctrls;
	}

	imx290_ctrl_update(imx290, imx290->current_mode);

1013
	return 0;
1014 1015 1016 1017 1018 1019

err_ctrls:
	v4l2_ctrl_handler_free(&imx290->ctrls);
err_media:
	media_entity_cleanup(&imx290->sd.entity);
	return ret;
1020 1021 1022 1023
}

static void imx290_subdev_cleanup(struct imx290 *imx290)
{
1024
	v4l2_subdev_cleanup(&imx290->sd);
1025 1026 1027 1028
	media_entity_cleanup(&imx290->sd.entity);
	v4l2_ctrl_handler_free(&imx290->ctrls);
}

1029 1030 1031
/* ----------------------------------------------------------------------------
 * Power management
 */
1032

1033 1034
static int imx290_power_on(struct device *dev)
{
1035
	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1036 1037 1038 1039 1040
	struct imx290 *imx290 = to_imx290(sd);
	int ret;

	ret = clk_prepare_enable(imx290->xclk);
	if (ret) {
1041
		dev_err(dev, "Failed to enable clock\n");
1042 1043 1044
		return ret;
	}

1045 1046
	ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies),
				    imx290->supplies);
1047
	if (ret) {
1048
		dev_err(dev, "Failed to enable regulators\n");
1049 1050 1051 1052 1053
		clk_disable_unprepare(imx290->xclk);
		return ret;
	}

	usleep_range(1, 2);
1054
	gpiod_set_value_cansleep(imx290->rst_gpio, 0);
1055 1056
	usleep_range(30000, 31000);

1057 1058 1059
	/* Set data lane count */
	imx290_set_data_lanes(imx290);

1060 1061 1062 1063 1064
	return 0;
}

static int imx290_power_off(struct device *dev)
{
1065
	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1066 1067 1068
	struct imx290 *imx290 = to_imx290(sd);

	clk_disable_unprepare(imx290->xclk);
1069
	gpiod_set_value_cansleep(imx290->rst_gpio, 1);
1070
	regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies);
1071 1072 1073 1074 1075

	return 0;
}

static const struct dev_pm_ops imx290_pm_ops = {
1076
	SET_RUNTIME_PM_OPS(imx290_power_off, imx290_power_on, NULL)
1077 1078
};

1079 1080 1081
/* ----------------------------------------------------------------------------
 * Probe & remove
 */
1082

1083 1084 1085
static const struct regmap_config imx290_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
1086 1087
};

1088 1089 1090 1091
static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = {
	"vdda",
	"vddd",
	"vdddo",
1092 1093
};

1094
static int imx290_get_regulators(struct device *dev, struct imx290 *imx290)
1095
{
1096
	unsigned int i;
1097

1098 1099
	for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++)
		imx290->supplies[i].supply = imx290_supply_name[i];
1100

1101 1102
	return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies),
				       imx290->supplies);
1103 1104
}

1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132
static int imx290_init_clk(struct imx290 *imx290)
{
	u32 xclk_freq;
	int ret;

	ret = fwnode_property_read_u32(dev_fwnode(imx290->dev),
				       "clock-frequency", &xclk_freq);
	if (ret) {
		dev_err(imx290->dev, "Could not get xclk frequency\n");
		return ret;
	}

	/* external clock must be 37.125 MHz */
	if (xclk_freq != 37125000) {
		dev_err(imx290->dev, "External clock frequency %u is not supported\n",
			xclk_freq);
		return -EINVAL;
	}

	ret = clk_set_rate(imx290->xclk, xclk_freq);
	if (ret) {
		dev_err(imx290->dev, "Could not set xclk frequency\n");
		return ret;
	}

	return 0;
}

1133 1134 1135 1136 1137
/*
 * Returns 0 if all link frequencies used by the driver for the given number
 * of MIPI data lanes are mentioned in the device tree, or the value of the
 * first missing frequency otherwise.
 */
1138 1139
static s64 imx290_check_link_freqs(const struct imx290 *imx290,
				   const struct v4l2_fwnode_endpoint *ep)
1140 1141 1142 1143 1144 1145
{
	int i, j;
	const s64 *freqs = imx290_link_freqs_ptr(imx290);
	int freqs_count = imx290_link_freqs_num(imx290);

	for (i = 0; i < freqs_count; i++) {
1146 1147
		for (j = 0; j < ep->nr_of_link_frequencies; j++)
			if (freqs[i] == ep->link_frequencies[j])
1148
				break;
1149
		if (j == ep->nr_of_link_frequencies)
1150 1151 1152 1153 1154
			return freqs[i];
	}
	return 0;
}

1155
static int imx290_parse_dt(struct imx290 *imx290)
1156
{
1157 1158 1159 1160
	/* Only CSI2 is supported for now: */
	struct v4l2_fwnode_endpoint ep = {
		.bus_type = V4L2_MBUS_CSI2_DPHY
	};
1161
	struct fwnode_handle *endpoint;
1162
	int ret;
1163
	s64 fq;
1164

1165
	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL);
1166
	if (!endpoint) {
1167
		dev_err(imx290->dev, "Endpoint node not found\n");
1168 1169 1170
		return -EINVAL;
	}

1171
	ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep);
1172
	fwnode_handle_put(endpoint);
1173
	if (ret == -ENXIO) {
1174 1175
		dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n");
		goto done;
1176
	} else if (ret) {
1177 1178
		dev_err(imx290->dev, "Parsing endpoint node failed\n");
		goto done;
1179 1180
	}

1181
	/* Get number of data lanes */
1182
	imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes;
1183
	if (imx290->nlanes != 2 && imx290->nlanes != 4) {
1184
		dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes);
1185
		ret = -EINVAL;
1186
		goto done;
1187 1188
	}

1189
	dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes);
1190

1191
	if (!ep.nr_of_link_frequencies) {
1192
		dev_err(imx290->dev, "link-frequency property not found in DT\n");
1193
		ret = -EINVAL;
1194
		goto done;
1195 1196
	}

1197
	/* Check that link frequences for all the modes are in device tree */
1198
	fq = imx290_check_link_freqs(imx290, &ep);
1199
	if (fq) {
1200 1201
		dev_err(imx290->dev, "Link frequency of %lld is not supported\n",
			fq);
1202
		ret = -EINVAL;
1203
		goto done;
1204 1205
	}

1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
	ret = 0;

done:
	v4l2_fwnode_endpoint_free(&ep);
	return ret;
}

static int imx290_probe(struct i2c_client *client)
{
	struct device *dev = &client->dev;
	struct imx290 *imx290;
	int ret;

	imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL);
	if (!imx290)
		return -ENOMEM;

	imx290->dev = dev;
	imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config);
	if (IS_ERR(imx290->regmap)) {
		dev_err(dev, "Unable to initialize I2C\n");
		return -ENODEV;
	}

	ret = imx290_parse_dt(imx290);
	if (ret)
		return ret;

1234
	/* Acquire resources. */
1235
	imx290->xclk = devm_clk_get(dev, "xclk");
1236 1237 1238
	if (IS_ERR(imx290->xclk))
		return dev_err_probe(dev, PTR_ERR(imx290->xclk),
				     "Could not get xclk");
1239 1240

	ret = imx290_get_regulators(dev, imx290);
1241 1242
	if (ret < 0)
		return dev_err_probe(dev, ret, "Cannot get regulators\n");
1243

1244 1245
	imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset",
						   GPIOD_OUT_HIGH);
1246 1247 1248
	if (IS_ERR(imx290->rst_gpio))
		return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio),
				     "Cannot get reset gpio\n");
1249

1250 1251 1252 1253 1254 1255
	/* Initialize external clock frequency. */
	ret = imx290_init_clk(imx290);
	if (ret)
		return ret;

	/* Initialize and register subdev. */
1256 1257
	ret = imx290_subdev_init(imx290);
	if (ret)
1258
		return ret;
1259 1260 1261 1262

	ret = v4l2_async_register_subdev(&imx290->sd);
	if (ret < 0) {
		dev_err(dev, "Could not register v4l2 device\n");
1263
		goto err_subdev;
1264 1265 1266 1267 1268 1269
	}

	/* Power on the device to match runtime PM state below */
	ret = imx290_power_on(dev);
	if (ret < 0) {
		dev_err(dev, "Could not power on the device\n");
1270
		goto err_subdev;
1271 1272 1273 1274 1275 1276 1277 1278
	}

	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);
	pm_runtime_idle(dev);

	return 0;

1279 1280
err_subdev:
	imx290_subdev_cleanup(imx290);
1281 1282 1283 1284

	return ret;
}

1285
static void imx290_remove(struct i2c_client *client)
1286 1287 1288 1289 1290
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct imx290 *imx290 = to_imx290(sd);

	v4l2_async_unregister_subdev(sd);
1291
	imx290_subdev_cleanup(imx290);
1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320

	pm_runtime_disable(imx290->dev);
	if (!pm_runtime_status_suspended(imx290->dev))
		imx290_power_off(imx290->dev);
	pm_runtime_set_suspended(imx290->dev);
}

static const struct of_device_id imx290_of_match[] = {
	{ .compatible = "sony,imx290" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx290_of_match);

static struct i2c_driver imx290_i2c_driver = {
	.probe_new  = imx290_probe,
	.remove = imx290_remove,
	.driver = {
		.name  = "imx290",
		.pm = &imx290_pm_ops,
		.of_match_table = of_match_ptr(imx290_of_match),
	},
};

module_i2c_driver(imx290_i2c_driver);

MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver");
MODULE_AUTHOR("FRAMOS GmbH");
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
MODULE_LICENSE("GPL v2");