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Julius Werner authored
We have found that we can sometimes see read failures on boards with high-capacitance SPI lines. It seems that the controller samples the Rx data line too early, and its register interface has an "Rx Sample Delay" setting to fine-tune against this issue. This patch adds a new optional device tree entry that can configure this delay in terms of nanoseconds. The kernel will calculate the best-fitting amount of parent clock ticks to program the controller with based on that. Signed-off-by:
Julius Werner <jwerner@chromium.org> Signed-off-by:
Mark Brown <broonie@kernel.org>
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