• Chris Wilson's avatar
    drm/i915: Write RING_TAIL once per-request · 09246732
    Chris Wilson authored
    Ignoring the legacy DRI1 code, and a couple of special cases (to be
    discussed later), all access to the ring is mediated through requests.
    The first write to a ring will grab a seqno and mark the ring as having
    an outstanding_lazy_request. Either through explicitly adding a request
    after an execbuffer or through an implicit wait (either by the CPU or by
    a semaphore), that sequence of writes will be terminated with a request.
    So we can ellide all the intervening writes to the tail register and
    send the entire command stream to the GPU at once. This will reduce the
    number of *serialising* writes to the tail register by a factor or 3-5
    times (depending upon architecture and number of workarounds, context
    switches, etc involved). This becomes even more noticeable when the
    register write is overloaded with a number of debugging tools. The
    astute reader will wonder if it is then possible to overflow the ring
    with a single command. It is not. When we start a command sequence to
    the ring, we check for available space and issue a wait in case we have
    not. The ring wait will in this case be forced to flush the outstanding
    register write and then poll the ACTHD for sufficient space to continue.
    
    The exception to the rule where everything is inside a request are a few
    initialisation cases where we may want to write GPU commands via the CS
    before userspace wakes up and page flips.
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    09246732
intel_display.c 294 KB