• Ben Widawsky's avatar
    drm/i915/hsw: Set correct Haswell PTE encodings. · 0d8ff15e
    Ben Widawsky authored
    The cacheability controls have changed, and the bits have been
    rearranged in general.
    
    Note that age 0 is the oldest (most likely to get evicted) and age 3
    is the youngest (most likely to stick around for a bit). We've picked
    0 for no reason, but atm it shouldn't matter anyway (since we don't
    yet try to differentiate between different objects).
    
    v2: Remove comments for snb/ivb cache leves, that's a separate change.
    
    v3: Resolve conflicts due to patch series reordering.
    
    v4: Rebased on top of Kenneth Graunke's ->pte_encode refactoring.
    
    v5: Removed eLLC bits for separate patch.
    
    In the internal repository this was:
    Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
    Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
    Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    [danvet: Add comment about cache ages as requested by Ben provoked due
    to a question from Damien.]
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    0d8ff15e
i915_gem_gtt.c 24.1 KB