• Andi Kleen's avatar
    perf/x86/intel: Add new cache events table for Haswell · 0f1b5ca2
    Andi Kleen authored
    Haswell offcore events are quite different from Sandy Bridge.
    Add a new table to handle Haswell properly.
    
    Note that the offcore bits listed in the SDM are not quite correct
    (this is currently being fixed). An uptodate list of bits is
    in the patch.
    
    The basic setup is similar to Sandy Bridge. The prefetch columns
    have been removed, as prefetch counting is not very reliable
    on Haswell. One L1 event that is not in the event list anymore
    has been also removed.
    
    - data reads do not include code reads (comparable to earlier Sandy Bridge tables)
    - data counts include speculative execution (except L1 write, dtlb, bpu)
    - remote node access includes both remote memory, remote cache, remote mmio.
    - prefetches are not included in the counts for consistency
      (different from Sandy Bridge, which includes prefetches in the remote node)
    Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
    [ Removed the HSM30 comments; we don't have them for SNB/IVB either. ]
    Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
    Link: http://lkml.kernel.org/r/1424225886-18652-1-git-send-email-andi@firstfloor.orgSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    0f1b5ca2
perf_event_intel.c 78.6 KB