The display pipeline has the same structure, resources and connections
on both the A23 and A33. The differences include:

  - compatible strings
  - extra clock, reset control, and IO region for SAT in the backend
    only found on the A33
  - missing ch1 clock for the TCON

However, while the A23 has the TCON ch1 clock defined in the CCU, and
the channel 1 registers are available, it does not have any means to
use channel 1 due to a lack of downstream encoders, and the enable bit
for channel 1 is hard-wired to 0 (off).

As the MIPI DSI output device is not officially documented, and there
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>