• Carl E. Love's avatar
    powerpc/perf_event: Fix Power6 L1 cache read & write event codes] · d15f02eb
    Carl E. Love authored
    The current L1 cache read event code 0x80082 only counts for thread 0. The
    event code 0x280030 should be used to count events on thread 0 and 1. The
    patch fixes the event code for the L1 cache read.
    
    The current L1 cache write event code 0x80086 only counts for thread 0. The
    event code 0x180032 should be used to count events on thread 0 and 1. The
    patch fixes the event code for the L1 cache write.
    
    FYI, the documentation lists three event codes for the L1 cache read event
    and three event codes for the L1 cache write event.  The event description
    for the event codes is as follows:
    
    L1 cache read requests  0x80082  LSU 0 only
    L1 cache read requests  0x8008A  LSU 1 only
    L1 cache read requests  0x80030  LSU 1 or LSU 0, counter 2 only.
    
    L1 cache store requests 0x80086  LSU 0 only
    L1 cache store requests 0x8008E  LSU 1 only
    L1 cache store requests 0x80032  LSU 0 or LSU 1, counter 1 only.
    
    There can only be one request from either LSU 0 or 1 active at a time.
    Signed-off-by: default avatarCarl Love <cel@us.ibm.com>
    Acked-by: default avatarPaul Mackerras <paulus@samba.org>
    Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
    d15f02eb
power6-pmu.c 15.5 KB