You need to sign in or sign up before continuing.
-
Satheeshakrishna M authored
Determine programmed cd clock for SKL. v2: Fix the LCPLL1 enable warning logic v3: Rebase over the hsw pll rework. v4: Rebase on top of the per-platform split (Damien) v5: Modified as per review comments from Paulo Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
121643c2