During plane operations, we read/write some registers that only operate
properly if we're not runtime suspended.  At the moment we're not
holding the runtime PM reference across the whole plane operation, so
there's a potential for problems.

This issue was already partially addressed by commit

        commit d6dd6843
        Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
        Date:   Fri Aug 15 15:59:32 2014 -0300

            drm/i915: fix plane/cursor handling when runtime suspended

which took care of holding the runtime PM reference during the pin and
fence operations for plane updates.  However there are still a few
actual plane registers that we also need to hold the runtime PM
reference for.  Recent refactoring patches in preparation for atomic
have rearranged the code and made it increasingly likely that the
hardware will have time to suspend between the pin/fence operation and
the actual register writes. Examples of such registers are the stuff
touched by ivb_get_colorkey.

The solution here grabs the runtime PM reference around the 'commit'
operation for planes, which should cover all the relevant register
reads/writes.

Note that this has only been exposed with

commit 6beb8c23
Author: Matt Roper <matthew.d.roper@intel.com>
Date:   Mon Dec 1 15:40:14 2014 -0800

    drm/i915: Consolidate plane 'prepare' functions (v2)

so doesn't need to be ported to 3.19.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87180Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Testcase: igt/pm-rpm/legacy-planes
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Augment commit message with information Paulo supplied.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>