There are a few clocks whose parents are set in mipi_dsi
and lcdif nodes, but these clocks are used by the media_blk_ctrl
power domain.  This may cause an issue when re-parenting, because
the media_blk_ctrl may start the clocks before the reparent is
done resulting in a disp_pixel clock having the wrong parent and
rate.

Fix this by moving the assigned-clock-parents and rates to the
media_blk_ctrl node to configure these clocks before they are enabled.

After this patch, both disp1_pix_root and dixp2_pix_root clock
become children of the video_pll1.

video_pll1_ref_sel           24000000
  video_pll1               1039500000
    video_pll1_bypass        1039500000
      video_pll1_out           1039500000
        media_disp2_pix          1039500000
          media_disp2_pix_root_clk   1039500000
        media_disp1_pix          1039500000
          media_disp1_pix_root_clk   1039500000

Fixes: eda09fe1 ("arm64: dts: imx8mp: Add display pipeline components")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>