• Aravind Gopalakrishnan's avatar
    amd64_edac: Add ECC decoding support for newer F15h models · 18b94f66
    Aravind Gopalakrishnan authored
    On newer models, support has been included for upto 4 DCT's, however,
    only DCT0 and DCT3 are currently configured (cf BKDG Section 2.10).
    Also, the routing DRAM Requests algorithm is different for F15h M30h.
    Thus it is cleaner to use a brand new function rather than adding quirks
    to the more generic f1x_match_to_this_node(). Refer to "2.10.5 DRAM
    Routing Requests" in the BKDG for further info.
    
    Tested on Fam15h M30h with ECC turned on using mce_amd_inj facility and
    verified to be functionally correct.
    
    While at it, verify if erratum workarounds for E505 and E637 still hold.
    From email conversations within AMD, the current status of the errata
    is:
    
          * Erratum 505: fixed in model 0x1, stepping 0x1 and later.
          * Erratum 637: not fixed.
    Signed-off-by: default avatarAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
    [ Cleanups, corrections ]
    Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
    18b94f66
amd64_edac.c 74.8 KB